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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-18 11:21:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-18 11:21:53 -0700 |
| commit | 4555b5b81981b74fa20909a72353d45e7be011ad (patch) | |
| tree | 5ca80102e513e17bc8138dbc46062fda7a65e7bb /passes | |
| parent | 8b12e97153a30cbc78d97a0f9ded26b653097949 (diff) | |
| download | yosys-4555b5b81981b74fa20909a72353d45e7be011ad.tar.gz yosys-4555b5b81981b74fa20909a72353d45e7be011ad.tar.bz2 yosys-4555b5b81981b74fa20909a72353d45e7be011ad.zip | |
kernel: more pass by const ref, more speedups
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/trace.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index cf3e46ace..8446e27b3 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -35,7 +35,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", log_id(module)); } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } |