diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 09:17:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 09:17:53 -0700 |
| commit | af16ca9dd4abdbb7c6a2f54f15abb493a4584ce6 (patch) | |
| tree | d1ba4ceb1c65fe7b5f0249c59506e601f04807b5 /passes | |
| parent | 81ca776ea44e126b3946fcdd076c2d2e4d2ab34d (diff) | |
| download | yosys-af16ca9dd4abdbb7c6a2f54f15abb493a4584ce6.tar.gz yosys-af16ca9dd4abdbb7c6a2f54f15abb493a4584ce6.tar.bz2 yosys-af16ca9dd4abdbb7c6a2f54f15abb493a4584ce6.zip | |
opt_expr: fix missing brace
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index f9bf3c194..4163c31f0 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -502,7 +502,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons SigBit sig_b = assign_map(cell->getPort(ID::B)); if (!sig_a.wire) std::swap(sig_a, sig_b); - if (sig_b == State::S0 || sig_b == State::S1) + if (sig_b == State::S0 || sig_b == State::S1) { if (cell->type.in(ID($xor), ID($_XOR_))) { cover("opt.opt_expr.xor_buffer"); replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); @@ -510,9 +510,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.xnor_buffer"); - replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); + replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); goto next_cell; } + log_abort(); + } } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) && |