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author | Eddie Hung <eddie@fpgeh.com> | 2020-03-30 11:13:06 -0700 |
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committer | GitHub <noreply@github.com> | 2020-03-30 11:13:06 -0700 |
commit | 769c7318e7b6dea9fbc4d7ba261f3df022f46d77 (patch) | |
tree | f8eda6546f1450fe9cab6f8d5e4709c5885ce1c3 /passes | |
parent | d5e2061687991085de89acc1905a366abd263c90 (diff) | |
parent | 9f265dfd3f9ae087fa22ffd809c00625fc6e2c65 (diff) | |
download | yosys-769c7318e7b6dea9fbc4d7ba261f3df022f46d77.tar.gz yosys-769c7318e7b6dea9fbc4d7ba261f3df022f46d77.tar.bz2 yosys-769c7318e7b6dea9fbc4d7ba261f3df022f46d77.zip |
Merge pull request #1833 from boqwxp/cleanup_sat_freduce
Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
Diffstat (limited to 'passes')
-rw-r--r-- | passes/sat/freduce.cc | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index f29631639..54016e528 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -614,29 +614,29 @@ struct FreduceWorker int bits_full_total = 0; std::vector<std::set<RTLIL::SigBit>> batches; - for (auto &it : module->wires_) - if (it.second->port_input) { - batches.push_back(sigmap(it.second).to_sigbit_set()); - bits_full_total += it.second->width; + for (auto w : module->wires()) + if (w->port_input) { + batches.push_back(sigmap(w).to_sigbit_set()); + bits_full_total += w->width; } - for (auto &it : module->cells_) { - if (ct.cell_known(it.second->type)) { + for (auto cell : module->cells()) { + if (ct.cell_known(cell->type)) { std::set<RTLIL::SigBit> inputs, outputs; - for (auto &port : it.second->connections()) { + for (auto &port : cell->connections()) { std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector(); - if (ct.cell_output(it.second->type, port.first)) + if (ct.cell_output(cell->type, port.first)) outputs.insert(bits.begin(), bits.end()); else inputs.insert(bits.begin(), bits.end()); } - std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs); + std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs); for (auto &bit : outputs) drivers[bit] = drv; batches.push_back(outputs); bits_full_total += outputs.size(); } - if (inv_mode && it.second->type == "$_NOT_") - inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y")))); + if (inv_mode && cell->type == "$_NOT_") + inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y")))); } int bits_count = 0; @@ -828,10 +828,8 @@ struct FreducePass : public Pass { extra_args(args, argidx, design); int bitcount = 0; - for (auto &mod_it : design->modules_) { - RTLIL::Module *module = mod_it.second; - if (design->selected(module)) - bitcount += FreduceWorker(design, module).run(); + for (auto module : design->selected_modules()) { + bitcount += FreduceWorker(design, module).run(); } log("Rewired a total of %d signal bits.\n", bitcount); |