| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | Refactored extract_counter to be generic vs GreenPAK specific | Andrew Zonenberg | 2017-08-28 | 1 | -51/+87 |
| | * | Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ... | Andrew Zonenberg | 2017-08-28 | 2 | -0/+514 |
| * | | Update more stuff to use get_src_attribute() and set_src_attribute() | Clifford Wolf | 2017-09-01 | 1 | -4/+4 |
| * | | updated to use get_src_attribute() and set_src_attribute(). | Jason Lowdermilk | 2017-08-31 | 3 | -10/+7 |
| * | | Add support for source line tracking through synthesis phase | Jason Lowdermilk | 2017-08-29 | 3 | -4/+23 |
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| * | Rename recover_reduce to extract_reduce, fix args handling | Clifford Wolf | 2017-08-28 | 2 | -8/+25 |
| * | Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azo... | Clifford Wolf | 2017-08-28 | 2 | -0/+223 |
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| | * | recover_reduce: Update documentation | Robert Ou | 2017-08-27 | 1 | -8/+11 |
| | * | recover_reduce: Reindent using tabs | Robert Ou | 2017-08-27 | 1 | -190/+190 |
| | * | recover_reduce: Rename recover_reduce_core to recover_reduce | Robert Ou | 2017-08-27 | 3 | -101/+0 |
| | * | recover_reduce: Add driver script for the $reduce_* recover feature | Robert Ou | 2017-08-27 | 2 | -0/+101 |
| | * | recover_reduce_core: Finish implementing the core function | Robert Ou | 2017-08-27 | 1 | -0/+110 |
| | * | recover_reduce_core: Initial commit | Robert Ou | 2017-08-27 | 2 | -0/+110 |
| * | | Further improve extract_fa pass | Clifford Wolf | 2017-08-28 | 1 | -1/+42 |
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| * | Don't track , ... contradictions through x/z-bits | Clifford Wolf | 2017-08-25 | 1 | -1/+4 |
| * | Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr | Clifford Wolf | 2017-08-25 | 1 | -0/+72 |
| * | Further improve extract_fa (seems to be fully functional now) | Clifford Wolf | 2017-08-25 | 1 | -10/+226 |
| * | Rename "adders" to "extract_fa" | Clifford Wolf | 2017-08-25 | 2 | -28/+16 |
| * | Towards more generic "adder" function extractor | Clifford Wolf | 2017-08-23 | 1 | -202/+53 |
| * | Add experimental adders pass | Clifford Wolf | 2017-08-22 | 2 | -0/+447 |
| * | Remove some dead code from fsm_map | Clifford Wolf | 2017-08-21 | 1 | -3/+0 |
| * | Rename "singleton" pass to "uniquify" | Clifford Wolf | 2017-08-20 | 3 | -21/+22 |
| * | More intuitive handling of "cd .." for singleton modules | Clifford Wolf | 2017-08-19 | 1 | -2/+38 |
| * | Add "sim -zinit -rstlen" | Clifford Wolf | 2017-08-18 | 1 | -1/+53 |
| * | Add "sim" support for memories | Clifford Wolf | 2017-08-18 | 1 | -2/+136 |
| * | Add support for assert/assume/cover to "sim" command | Clifford Wolf | 2017-08-18 | 1 | -4/+47 |
| * | Add writeback mode to "sim" command | Clifford Wolf | 2017-08-17 | 1 | -0/+44 |
| * | Improve "sim" command | Clifford Wolf | 2017-08-17 | 1 | -54/+272 |
| * | Add "sim" command skeleton | Clifford Wolf | 2017-08-16 | 2 | -0/+372 |
| * | Mostly coding style related fixes in rmports pass | Clifford Wolf | 2017-08-15 | 1 | -30/+33 |
| * | Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg... | Clifford Wolf | 2017-08-15 | 2 | -0/+185 |
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| | * | rmports: Now remove ports from cell instances if we optimized them out of tha... | Andrew Zonenberg | 2017-08-14 | 1 | -2/+35 |
| | * | ProcessModule is no longer virtual (why was it in the first place?) | Andrew Zonenberg | 2017-08-14 | 1 | -1/+1 |
| | * | rmports now works on all modules in the design, not just the top. | Andrew Zonenberg | 2017-08-14 | 1 | -4/+7 |
| | * | Updated Makefile to reflect opt_rmports being renamed to rmports | Andrew Zonenberg | 2017-08-14 | 1 | -1/+1 |
| | * | Renamed opt_rmports pass to rmports | Andrew Zonenberg | 2017-08-14 | 1 | -5/+5 |
| | * | Improved handling of constant connections in opt_rmports | Andrew Zonenberg | 2017-08-14 | 1 | -0/+2 |
| | * | Fixed handling of cell ports that aren't wires | Andrew Zonenberg | 2017-08-14 | 1 | -0/+3 |
| | * | opt_rmports: Fixed incorrect handling of multi-bit nets | Andrew Zonenberg | 2017-08-14 | 1 | -12/+27 |
| | * | Removed commented out debug code | Andrew Zonenberg | 2017-08-14 | 1 | -4/+0 |
| | * | Added opt_rmports pass (remove unconnected ports from top-level modules) | Andrew Zonenberg | 2017-08-14 | 2 | -0/+133 |
| * | | abc: Allow +/ filenames in the abc command | Robert Ou | 2017-08-14 | 1 | -0/+3 |
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| * | Add support for set-reset cell variants to opt_rmdff | Clifford Wolf | 2017-08-09 | 1 | -0/+182 |
| * | Add handling of constant reset signals to opt_rmdff | Clifford Wolf | 2017-08-06 | 1 | -1/+23 |
| * | Fix typo in "abc" pass help message | Clifford Wolf | 2017-07-29 | 1 | -1/+1 |
| * | Add consolidation of init attributes to opt_clean, some opt_clean log fixes | Clifford Wolf | 2017-07-29 | 1 | -6/+82 |
| * | Add "opt_expr -fine" feature to remove neutral bits from reduce and logic ope... | Clifford Wolf | 2017-07-26 | 1 | -0/+47 |
| * | Add error for cell output ports that are connected to constants | Clifford Wolf | 2017-07-22 | 1 | -20/+21 |
| * | Fix handling of empty cell port assignments (i.e. ignore them) | Clifford Wolf | 2017-07-21 | 2 | -0/+6 |
| * | Add $alu to list of supported cells for "stat -width" | Clifford Wolf | 2017-07-14 | 1 | -1/+1 |
