Add support for source line tracking through synthesis phase

3 files changed, 23 insertions, 4 deletions

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 9f6dd02d0..9593ef27a 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -55,19 +55,19 @@ struct AlumaccWorker
 
 		RTLIL::SigSpec get_gt() {
 			if (GetSize(cached_gt) == 0)
-				cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()));
+				cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->attributes["\\src"].decode_string());
 			return cached_gt;
 		}
 
 		RTLIL::SigSpec get_eq() {
 			if (GetSize(cached_eq) == 0)
-				cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"));
+				cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->attributes["\\src"].decode_string());
 			return cached_eq;
 		}
 
 		RTLIL::SigSpec get_ne() {
 			if (GetSize(cached_ne) == 0)
-				cached_ne = alu_cell->module->Not(NEW_ID, get_eq());
+				cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->attributes["\\src"].decode_string());
 			return cached_ne;
 		}
 
@@ -75,7 +75,7 @@ struct AlumaccWorker
 			if (GetSize(cached_cf) == 0) {
 				cached_cf = alu_cell->getPort("\\CO");
 				log_assert(GetSize(cached_cf) >= 1);
-				cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1]);
+				cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->attributes["\\src"].decode_string());
 			}
 			return cached_cf;
 		}
@@ -352,10 +352,14 @@ struct AlumaccWorker
 		{
 			auto n = it.second;
 			auto cell = module->addCell(NEW_ID, "$macc");
+			auto src = n->cell->attributes["\\src"].decode_string();
+
 			macc_counter++;
 
 			log("  creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
 
+			if (!src.empty()) cell->attributes["\\src"] = src;
+
 			n->macc.optimize(GetSize(n->y));
 			n->macc.to_cell(cell);
 			cell->setPort("\\Y", n->y);
@@ -452,6 +456,7 @@ struct AlumaccWorker
 
 	void replace_alu()
 	{
+		std::string src("");
 		for (auto &it1 : sig_alu)
 		for (auto n : it1.second)
 		{
@@ -475,6 +480,9 @@ struct AlumaccWorker
 				log("%s%s", i ? ", ": "", log_id(n->cells[i]));
 			log(": %s\n", log_id(n->alu_cell));
 
+			src = n->cells.size() > 0 ? n->cells[0]->attributes["\\src"].decode_string() : "";
+			if (!src.empty()) n->alu_cell->attributes["\\src"] = src;
+
 			n->alu_cell->setPort("\\A", n->a);
 			n->alu_cell->setPort("\\B", n->b);
 			n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index c8104fb7e..71d708c18 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -478,11 +478,15 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
 		auto cell_type = cell->type;
 		auto cell_name = cell->name;
 		auto cell_connections = cell->connections();
+		std::string src = cell->attributes["\\src"].decode_string();
+
 		module->remove(cell);
 
 		cell_mapping &cm = cell_mappings[cell_type];
 		RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
 
+		if (!src.empty()) new_cell->attributes["\\src"] = src;
+
 		bool has_q = false, has_qn = false;
 		for (auto &port : cm.ports) {
 			if (port.second == 'Q') has_q = true;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index ae89453d0..acc5d7471 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -172,6 +172,7 @@ struct TechmapWorker
 
 		std::string orig_cell_name;
 		pool<string> extra_src_attrs;
+		std::string src = cell->attributes["\\src"].decode_string();
 
 		if (!flatten_mode)
 		{
@@ -340,6 +341,8 @@ struct TechmapWorker
 			RTLIL::Cell *c = module->addCell(c_name, it.second);
 			design->select(module, c);
 
+			if (!src.empty()) c->attributes["\\src"] = src;
+
 			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
 				c->type = c->type.substr(1);
 
@@ -464,7 +467,9 @@ struct TechmapWorker
 			log_assert(cell == module->cell(cell->name));
 			bool mapped_cell = false;
 
+			std::string src       = cell->attributes["\\src"].decode_string();
 			std::string cell_type = cell->type.str();
+
 			if (in_recursion && cell_type.substr(0, 2) == "\\$")
 				cell_type = cell_type.substr(1);
 
@@ -512,6 +517,8 @@ struct TechmapWorker
 								extmapper_module = extmapper_design->addModule(m_name);
 								RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
 
+								if (!src.empty()) extmapper_cell->attributes["\\src"] = src;
+
 								int port_counter = 1;
 								for (auto &c : extmapper_cell->connections_) {
 									RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));