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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-21 19:32:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-21 19:32:31 +0200 |
| commit | b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb (patch) | |
| tree | 6479759cc374b0306b812f90db1a754ff52f1ec6 /passes | |
| parent | 36cf18ac4c1f96cad795032c3597abf08af6a6d8 (diff) | |
| download | yosys-b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb.tar.gz yosys-b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb.tar.bz2 yosys-b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb.zip | |
Fix handling of empty cell port assignments (i.e. ignore them)
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 3 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index d71e9c574..41c1cfded 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -640,6 +640,9 @@ struct HierarchyPass : public Pass { if (w == nullptr || w->port_id == 0) continue; + if (GetSize(conn.second) == 0) + continue; + if (GetSize(w) == GetSize(conn.second)) continue; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e85714b57..ae89453d0 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -247,6 +247,9 @@ struct TechmapWorker continue; } + if (GetSize(it.second) == 0) + continue; + RTLIL::Wire *w = tpl->wires_.at(portname); RTLIL::SigSig c, extra_connect; |