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* Merge pull request #3280 from YosysHQ/micko/fix_readaiwMiodrag Milanović2022-04-181-2/+2
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| * Fix reading aiw from other solversMiodrag Milanovic2022-04-151-2/+2
* | memory_share: Fix up mismatched address widths.Marcelina Kościelnicka2022-04-151-0/+14
* | opt_dff: Fix behavior on $ff with D == Q.Marcelina Kościelnicka2022-04-151-1/+1
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* Use wrap_async_control_gate if ff is fineMiodrag Milanovic2022-04-081-9/+11
* Makefile: properly conditionalize features requiring compression.Iris Johnson2022-04-071-0/+2
* Merge pull request #3269 from YosysHQ/micko/fix_autotopCatherine2022-04-071-13/+13
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| * Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
* | abc: Add support for FFs with reset in -dffMarcelina Kościelnicka2022-04-071-90/+229
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* show: Fix width labels.Marcelina Kościelnicka2022-04-041-23/+18
* past_ad initial value settingMiodrag Milanovic2022-04-021-0/+3
* setInitState can be only one altering valuesMiodrag Milanovic2022-04-021-4/+6
* Set past_d value for init stateMiodrag Milanovic2022-04-021-0/+2
* Merge pull request #3264 from jix/invalid_ff_dcinit_mergeJannis Harder2022-04-022-2/+21
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| * opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-012-2/+21
* | Set init values for wrapped async control signalsMiodrag Milanovic2022-04-011-0/+2
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* Support memories in aiw and multiclockMiodrag Milanovic2022-03-311-16/+86
* Merge pull request #3194 from Ravenslofty/abc9-flow3mfsLofty2022-03-281-1/+7
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| * abc9: add flow3mfs scriptLofty2022-02-101-1/+7
* | abc9_ops: Also derive blackboxes with timing infogatecat2022-03-241-5/+10
* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
* | More verbose warningsMiodrag Milanovic2022-03-181-5/+7
* | Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-161-6/+32
* | Update sim help message.Miodrag Milanovic2022-03-161-1/+2
* | Merge pull request #3232 from YosysHQ/micko/fst2tbMiodrag Milanović2022-03-141-0/+319
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| * | Added fst2tb pass for generating testbenchMiodrag Milanovic2022-03-141-0/+319
* | | Merge pull request #3213 from antonblanchard/abc-typoClaire Xen2022-03-141-2/+2
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| * | abc: Fix {I} and {P} substitutionAnton Blanchard2022-02-231-2/+2
* | | Merge pull request #3229 from YosysHQ/micko/sim_dateMiodrag Milanović2022-03-111-7/+20
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| * | | Add date parameter to enable full date/time and version infoMiodrag Milanovic2022-03-111-7/+20
* | | | Add "sim -q" optionClaire Xenia Wolf2022-03-111-8/+19
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* | | Small fix in "sim" help messageClaire Xenia Wolf2022-03-111-1/+1
* | | FstData already do conversion to VCDMiodrag Milanovic2022-03-111-1/+2
* | | Support cell name in btor witness fileMiodrag Milanovic2022-03-111-5/+14
* | | Proper write of memory dataMiodrag Milanovic2022-03-111-14/+13
* | | Start work on memory initMiodrag Milanovic2022-03-091-9/+34
* | | Fixes and error checkMiodrag Milanovic2022-03-091-1/+5
* | | cleanupMiodrag Milanovic2022-03-071-1/+2
* | | Error checks for aiger witnessMiodrag Milanovic2022-03-071-0/+7
* | | btor2 witness co-simulationMiodrag Milanovic2022-03-071-8/+123
* | | Merge pull request #3219 from YosysHQ/micko/quick_vcdMiodrag Milanović2022-03-041-0/+1
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| * | | VCD reader support by using external toolMiodrag Milanovic2022-02-281-0/+1
* | | | Add option to ignore X only signals in outputMiodrag Milanovic2022-03-021-8/+32
* | | | Write simulation files after simulation is performedMiodrag Milanovic2022-03-021-145/+151
* | | | CleanupMiodrag Milanovic2022-03-021-10/+7
* | | | Refactor sim output writersMiodrag Milanovic2022-02-281-213/+257
* | | | Quick fixMiodrag Milanovic2022-02-281-0/+2
* | | | Add writing of aiw files to "sim" commandClaire Xenia Wolf2022-02-281-1/+87
* | | | Hotfix in AIGER witness reader state machineClaire Xenia Wolf2022-02-281-0/+1
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