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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-28 11:40:06 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-28 11:40:06 +0100 |
| commit | dfd4c81eac47bd06fc4f419c43e6fe508b4252df (patch) | |
| tree | f8c51629f91d2f1363449aaeeb54398253c52da3 /passes | |
| parent | 56b968f61c01600fde97f1b9b8e857b0f6ecd16d (diff) | |
| download | yosys-dfd4c81eac47bd06fc4f419c43e6fe508b4252df.tar.gz yosys-dfd4c81eac47bd06fc4f419c43e6fe508b4252df.tar.bz2 yosys-dfd4c81eac47bd06fc4f419c43e6fe508b4252df.zip | |
Quick fix
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 304dfef13..1ce563ac2 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1304,6 +1304,8 @@ struct SimWorker : SimShared state = 3; break; default: + log("Simulating cycle %d.\n", cycle); + top->setState(inputs, line); if (cycle) { set_inports(clock, State::S1); set_inports(clockn, State::S0); |