diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-22 14:22:32 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-22 14:22:32 +0100 |
| commit | ff3b0c2c4676a9b717929920fa27098c5f9b53e5 (patch) | |
| tree | 3b8577fc0ecd1b3ce29caa1f79ed42ec6f5c4e87 /passes | |
| parent | f45b2908203c42a9502d6bfa5f9a537a61efa6c8 (diff) | |
| download | yosys-ff3b0c2c4676a9b717929920fa27098c5f9b53e5.tar.gz yosys-ff3b0c2c4676a9b717929920fa27098c5f9b53e5.tar.bz2 yosys-ff3b0c2c4676a9b717929920fa27098c5f9b53e5.zip | |
Proper SigBit forming in sim
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sim.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index f225ebd15..b56ccb987 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1138,13 +1138,13 @@ struct SimWorker : SimShared if (index < w->start_offset || index > w->start_offset + w->width) log_error("Index %d for wire %s is out of range\n", index, log_signal(w)); if (type == "input") { - inputs[variable] = {SigBit(w,index), false}; + inputs[variable] = {SigBit(w,index-w->start_offset), false}; } else if (type == "init") { - inits[variable] = {SigBit(w,index), false}; + inits[variable] = {SigBit(w,index-w->start_offset), false}; } else if (type == "latch") { - latches[variable] = {SigBit(w,index), false}; + latches[variable] = {SigBit(w,index-w->start_offset), false}; } else if (type == "invlatch") { - latches[variable] = {SigBit(w,index), true}; + latches[variable] = {SigBit(w,index-w->start_offset), true}; } } |