iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Revert "Make one check $shift(x)? only; change testcase to be 8b"	Eddie Hung	2019-09-13	1	-3/+2
*	Tidy up	Eddie Hung	2019-09-11	1	-10/+16
*	Fix UB	Eddie Hung	2019-09-11	1	-2/+2
*	Cope with presence of reset muxes too	Eddie Hung	2019-09-11	1	-4/+25
*	Cleanup	Eddie Hung	2019-09-11	1	-25/+22
*	Only display log message if did_something	Eddie Hung	2019-09-11	1	-1/+1
*	Rename dffmuxext -> dffmux, also remove constants in dff+mux	Eddie Hung	2019-09-11	4	-57/+91
*	Make one check $shift(x)? only; change testcase to be 8b	Eddie Hung	2019-09-06	1	-2/+3
*	Remove log_cell() calls	Eddie Hung	2019-09-04	1	-3/+0
*	Add peepopt_dffmuxext	Eddie Hung	2019-09-04	3	-0/+60
*	Adopt @cliffordwolf's suggestion	Eddie Hung	2019-09-03	1	-10/+3
*	Merge remote-tracking branch 'origin/master' into eddie/deferred_top	Eddie Hung	2019-09-03	8	-202/+618
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\| *	Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc	Eddie Hung	2019-09-01	1	-5/+0
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\| \| *	Do not restrict multiplier to unsigned	Eddie Hung	2019-08-30	1	-5/+0
\| * \|	Fix select command error msg, fixes issue #1081	Miodrag Milanovic	2019-09-01	1	-2/+2
\| * \|	Missing dep for test_pmgen	Eddie Hung	2019-08-30	1	-1/+1
\| * \|	Merge pull request #1340 from YosysHQ/eddie/abc_no_clean	Eddie Hung	2019-08-30	1	-16/+10
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\| \| *	Output has priority over input when stitching in abc9	Eddie Hung	2019-08-29	1	-13/+10
\| \| *	abc9 to not call "clean" at end of run (often called outside)	Eddie Hung	2019-08-29	1	-3/+0
\| * \|	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	Eddie Hung	2019-08-30	2	-2/+37
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\| \| *	Fix typo that's gone unnoticed for 5 months!?!	Eddie Hung	2019-08-29	1	-1/+1
\| * \|	Cleanup	Eddie Hung	2019-08-28	1	-4/+0
\| * \|	Account for D port being a constant	Eddie Hung	2019-08-28	1	-4/+4
\| * \|	No need to replace Q of slice since $shiftx is autoremove-d	Eddie Hung	2019-08-28	1	-1/+0
\| * \|	More cleanup	Eddie Hung	2019-08-28	1	-12/+14
\| * \|	More cleanup	Eddie Hung	2019-08-28	1	-9/+6
\| * \|	Do not use default_params dict, hardcode default values, cleanup	Eddie Hung	2019-08-28	2	-25/+21
\| * \|	Always generate if no match	Eddie Hung	2019-08-28	1	-1/+1
\| * \|	Rename test_pmgen arg xilinx_srl.{fixed,variable}	Eddie Hung	2019-08-28	1	-2/+2
\| * \|	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	Eddie Hung	2019-08-28	5	-89/+457
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\| * \| \|	Missing close bracket	Eddie Hung	2019-08-26	1	-1/+1
\| * \| \|	Revert "In sat: 'x' in init attr should not override constant"	Eddie Hung	2019-08-26	1	-2/+0
\| * \| \|	Remove leftover header	Eddie Hung	2019-08-26	1	-1/+0
\| * \| \|	Improve xilinx_srl.fixed generate, add .variable generate	Eddie Hung	2019-08-26	1	-26/+75
\| * \| \|	Account for maxsubcnt overflowing	Eddie Hung	2019-08-26	1	-1/+1
\| * \| \|	Add xilinx_srl_pm.variable to test_pmgen	Eddie Hung	2019-08-26	1	-0/+2
\| * \| \|	Populate generate for xilinx_srl.fixed pattern	Eddie Hung	2019-08-26	1	-22/+54
\| * \| \|	Add xilinx_srl_fixed, fix typos	Eddie Hung	2019-08-26	1	-2/+6
\| * \| \|	Create new $__XILINX_SHREG_ cell for variable length too	Eddie Hung	2019-08-23	1	-31/+30
\| * \| \|	Do not allow Q of last cell of variable length SRL to be (* keep *)	Eddie Hung	2019-08-23	1	-0/+1
\| * \| \|	Also add first.Q to chain_bits since variable length	Eddie Hung	2019-08-23	1	-0/+1
\| * \| \|	Do not enforce !EN_POLARITY on $dffe	Eddie Hung	2019-08-23	1	-2/+0
\| * \| \|	Create new cell for fixed length SRL	Eddie Hung	2019-08-23	1	-14/+22
\| * \| \|	Cleanup FDRE matching	Eddie Hung	2019-08-23	1	-45/+19
\| * \| \|	Oops don't need a finally block	Eddie Hung	2019-08-23	1	-5/+0
\| * \| \|	Keep track of bits in variable length chain, to check for taps	Eddie Hung	2019-08-23	1	-0/+12
\| * \| \|	Don't forget $dff has no EN	Eddie Hung	2019-08-23	1	-2/+4
\| * \| \|	Same for variable length	Eddie Hung	2019-08-23	1	-2/+10
\| * \| \|	Filter on en_port for fixed length	Eddie Hung	2019-08-23	1	-4/+24
\| * \| \|	Check clock is consistent	Eddie Hung	2019-08-23	1	-5/+25