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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 16:21:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 16:21:10 -0700 |
| commit | 83e2d87fb80cc5aed018b0f3409f256ef7f7b385 (patch) | |
| tree | b888bafc3b07c33522129cb68d26f77450f0c2ac /passes | |
| parent | f2d48142843f2ed8bc9f0e55197ba347d210a6e1 (diff) | |
| download | yosys-83e2d87fb80cc5aed018b0f3409f256ef7f7b385.tar.gz yosys-83e2d87fb80cc5aed018b0f3409f256ef7f7b385.tar.bz2 yosys-83e2d87fb80cc5aed018b0f3409f256ef7f7b385.zip | |
Keep track of bits in variable length chain, to check for taps
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index fcfa79ea6..d17799208 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -186,6 +186,11 @@ state <int> shiftx_width state <int> slice udata <int> minlen udata <vector<pair<Cell*,int>>> chain +udata <pool<SigBit>> chain_bits + +code + chain_bits.clear(); +endcode match shiftx select shiftx->type.in($shiftx) @@ -251,13 +256,20 @@ match next index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] filter port(next, clk_port) == port(first, clk_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port) + filter !chain_bits.count(port(next, \D)[idx]) set slice idx endmatch code if (next) { + chain_bits.insert(port(next, \Q)[slice]); chain.emplace_back(next, slice); if (GetSize(chain) < shiftx_width) subpattern(tail); } +finally + if (next) { + chain_bits.erase(port(next, \Q)[slice]); + chain.pop_back(); + } endcode |