aboutsummaryrefslogtreecommitdiffstats
path: root/passes
Commit message (Collapse)AuthorAgeFilesLines
* Started to implement real resource sharingClifford Wolf2014-07-192-0/+444
|
* Improved memory_share log messagesClifford Wolf2014-07-191-3/+3
|
* More verbose memory_share help messageClifford Wolf2014-07-191-0/+17
|
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-191-0/+180
|
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-191-4/+12
|
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-182-10/+240
|
* Improved seeding of color rng in show commandClifford Wolf2014-07-181-1/+3
|
* Only create collision detect logic in memory_share if necessaryClifford Wolf2014-07-181-4/+47
|
* Added memory_shareClifford Wolf2014-07-183-0/+266
|
* Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN portClifford Wolf2014-07-181-0/+15
|
* Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-171-5/+18
|
* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-171-1/+1
|
* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-171-1/+4
|
* improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-161-0/+80
|
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-163-38/+56
|
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-051-4/+24
|
* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-191-0/+5
|
* Added %D and %c select commandsClifford Wolf2014-06-141-2/+20
|
* fixed cell array handling of positional argumentsClifford Wolf2014-06-071-2/+11
|
* Add support for cell arraysClifford Wolf2014-06-071-0/+34
|
* added tee cmdClifford Wolf2014-06-032-0/+89
|
* Fixed log messages in memory_dffClifford Wolf2014-06-011-0/+2
|
* added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-282-3/+9
|
* be more verbose when techmap yielded processesJohann Glaser2014-05-261-1/+5
|
* Fixed bug in opt_reduce (see vloghammer issue_044)Clifford Wolf2014-05-121-1/+4
|
* fixed syntax error in dot file created by "show" commandClifford Wolf2014-05-101-1/+1
|
* Fixed performance problem in opt_mux with nets driven by many conflicting ↵Clifford Wolf2014-03-191-1/+6
| | | | drivers
* Small improvement in SAT log messagesClifford Wolf2014-03-131-3/+3
|
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-131-0/+1
|
* - kernel/register.h, kernel/driver.cc: refactor ↵Siesh1oo2014-03-123-3/+5
| | | | | | | rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
* OSX compatible creation of stdcells.inc, using code from ↵Clifford Wolf2014-03-111-2/+3
| | | | | | github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28)
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-114-3/+11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-111-1/+1
|
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-091-2/+3
|
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-091-2/+2
|
* Fixed bug in freduce commandClifford Wolf2014-03-071-0/+30
|
* Some minor code cleanups in freduce commandClifford Wolf2014-03-071-5/+5
|
* Added freduce -dumpClifford Wolf2014-03-061-1/+24
|
* Added freduce -stopClifford Wolf2014-03-061-3/+18
|
* Fixed undef handling in opt_reduceClifford Wolf2014-03-061-2/+2
|
* Added techmap -max_iter optionClifford Wolf2014-03-061-0/+10
|
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-031-2/+2
|
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-271-0/+1
|
* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-221-1/+1
|
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-211-2/+6
|
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-201-4/+21
|
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-201-0/+79
|
* Added "extract -map %<design_name>"Clifford Wolf2014-02-201-10/+30
|
* Added "design -push" and "design -pop"Clifford Wolf2014-02-201-8/+45
|
* Added connwrappers commandClifford Wolf2014-02-202-0/+206
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-13 06:52:26 +0000