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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-18 10:28:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-18 10:28:45 +0200 |
| commit | 309ae98246cf9ff115b7d95ae14991faf72a5a38 (patch) | |
| tree | 381bb0d7ca956d943d9b5002fe85d2b14e83f00c /passes | |
| parent | 2d69c309f9d4d3093eead620684a59e3804b3894 (diff) | |
| download | yosys-309ae98246cf9ff115b7d95ae14991faf72a5a38.tar.gz yosys-309ae98246cf9ff115b7d95ae14991faf72a5a38.tar.bz2 yosys-309ae98246cf9ff115b7d95ae14991faf72a5a38.zip | |
Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_reduce.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 1e91d1601..a0c7a027f 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -266,6 +266,21 @@ struct OptReduceWorker mem_wren_sigs.add(assign_map(cell->connections["\\D"])); } + bool keep_expanding_mem_wren_sigs = true; + while (keep_expanding_mem_wren_sigs) { + keep_expanding_mem_wren_sigs = false; + for (auto &cell_it : module->cells) { + RTLIL::Cell *cell = cell_it.second; + if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Y"]))) { + if (!mem_wren_sigs.check_all(assign_map(cell->connections["\\A"])) || + !mem_wren_sigs.check_all(assign_map(cell->connections["\\B"]))) + keep_expanding_mem_wren_sigs = true; + mem_wren_sigs.add(assign_map(cell->connections["\\A"])); + mem_wren_sigs.add(assign_map(cell->connections["\\B"])); + } + } + } + while (did_something) { did_something = false; |