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* flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| | | | Fixes #1475.
* flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
| | | | Fixes #1405.
* Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-041-3/+12
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| * Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
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* | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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* Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-6/+40
|\ | | | | Add -select option to aigmap
| * Add -select option to aigmapEddie Hung2019-09-301-6/+40
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* | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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* | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-1/+1
|\ | | | | Open aig frontend as binary file
| * Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
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* | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-291-3/+16
|\ \ | |/ |/| DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-3/+16
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* | Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-13/+17
|/ | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396.
* Revert abc9.ccEddie Hung2019-09-201-1/+1
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* Trim mismatched connection to be same (smallest) sizeEddie Hung2019-09-201-0/+6
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* Fix first testcase in #1391Eddie Hung2019-09-202-2/+2
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* Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added extractinv passMarcin Kościelnicki2019-09-192-0/+124
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* Explicitly order function argumentsEddie Hung2019-09-131-4/+15
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* Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-3/+26
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* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-1/+70
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* Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-42/+16
|\ | | | | Allow arrival times of sequential outputs to be specified to abc9
| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-16/+10
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| * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-1/+1
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| * | | Use a dummy box file if none specifiedEddie Hung2019-08-281-3/+8
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| * | | Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-174/+5
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| * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-284-88/+456
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| * | | | | CleanupEddie Hung2019-08-231-130/+59
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| * | | | | Merge branch 'eddie/fix_techmap' into xaig_arrivalEddie Hung2019-08-201-1/+1
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| * | | | | | techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
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| * | | | | | Remove sequential extensionEddie Hung2019-08-201-68/+20
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| * | | | | | retime_mode -> dff_modeEddie Hung2019-08-201-7/+7
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| * | | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXMEEddie Hung2019-08-201-65/+13
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-6/+6
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-191-1/+1
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| * | | | | | | | Remove debugEddie Hung2019-08-191-1/+1
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| * | | | | | | | Add (* abc_arrival *) attributeEddie Hung2019-08-191-1/+1
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| * | | | | | | | Move from cell attr to module attrEddie Hung2019-08-191-24/+64
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-1920-263/+263
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| * | | | | | | | | Use attributes instead of paramsEddie Hung2019-08-191-11/+25
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| * | | | | | | | | Set abc_flop and use it in toposortEddie Hung2019-08-191-31/+51
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| * | | | | | | | | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1627-1267/+1501
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| * | | | | | | | | | Error out if abc9 not called with -lut or -lutsEddie Hung2019-07-111-0/+3
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| * | | | | | | | | | Count $_NOT_ cells turned into $lutsEddie Hung2019-07-111-7/+2
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| * | | | | | | | | | WIP for fixing partitioning, temporarily do not partitionEddie Hung2019-07-111-12/+34
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| * | | | | | | | | | write_verilog with *.v extensionEddie Hung2019-07-101-1/+1
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| * | | | | | | | | | Remove -retime from abc9, revert to abc behav with separate clock/en domainsEddie Hung2019-07-101-29/+61
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-102-8/+22
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| * | | | | | | | | | | Also remove $__ABC_FF_Eddie Hung2019-07-011-1/+1
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