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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:40 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:40 -0700 |
commit | 44374b1b2b0dbc455c9e43d713e133d7d78a5e1a (patch) | |
tree | 7e2b502d6272e72fcd8de886a9af08d684805cc0 /passes/techmap | |
parent | c340fbfab23c582103402bbd812d9bca4510dc41 (diff) | |
download | yosys-44374b1b2b0dbc455c9e43d713e133d7d78a5e1a.tar.gz yosys-44374b1b2b0dbc455c9e43d713e133d7d78a5e1a.tar.bz2 yosys-44374b1b2b0dbc455c9e43d713e133d7d78a5e1a.zip |
"abc_padding" attr for blackbox outputs that were padded, remove them later
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/abc9.cc | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7eac08d17..aa473e67d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -606,7 +606,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri existing_cell = module->cell(c->name); log_assert(existing_cell); cell = module->addCell(remap_name(c->name), c->type); - module->swap_names(cell, existing_cell); } if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; @@ -642,8 +641,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } - for (auto cell : boxes) - module->remove(cell); + for (auto existing_cell : boxes) { + Cell *cell = module->cell(remap_name(existing_cell->name)); + if (cell) { + for (auto &conn : existing_cell->connections()) { + if (!conn.second.is_wire()) + continue; + Wire *wire = conn.second.as_wire(); + if (!wire->get_bool_attribute(ID(abc_padding))) + continue; + cell->unsetPort(conn.first); + log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second)); + } + module->swap_names(cell, existing_cell); + } + module->remove(existing_cell); + } // Copy connections (and rename) from mapped_mod to module for (auto conn : mapped_mod->connections()) { |