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* GrammarEddie Hung2019-12-301-1/+1
* iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-251-23/+68
* Interpret "abc9 -lut" as lut string only if [0-9:]Eddie Hung2019-12-181-19/+18
* iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-146/+97
* abc9: Fix breaking of SCCsDavid Shah2019-12-011-29/+40
* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-0/+41
* Fix #1496.Marcin Kościelnicki2019-11-181-4/+8
* flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
* flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
* Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-041-3/+12
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| * Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
* | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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* Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-6/+40
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| * Add -select option to aigmapEddie Hung2019-09-301-6/+40
* | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
* | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-1/+1
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| * Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
* | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-291-3/+16
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| * "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-3/+16
* | Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-13/+17
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* Revert abc9.ccEddie Hung2019-09-201-1/+1
* Trim mismatched connection to be same (smallest) sizeEddie Hung2019-09-201-0/+6
* Fix first testcase in #1391Eddie Hung2019-09-202-2/+2
* Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
* Added extractinv passMarcin Kościelnicki2019-09-192-0/+124
* Explicitly order function argumentsEddie Hung2019-09-131-4/+15
* Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-3/+26
* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-1/+70
* Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-42/+16
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-16/+10
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| * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-1/+1
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| * | | Use a dummy box file if none specifiedEddie Hung2019-08-281-3/+8
| * | | Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-174/+5
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| * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-284-88/+456
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| * | | | | CleanupEddie Hung2019-08-231-130/+59
| * | | | | Merge branch 'eddie/fix_techmap' into xaig_arrivalEddie Hung2019-08-201-1/+1
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| * | | | | | techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
| * | | | | | Remove sequential extensionEddie Hung2019-08-201-68/+20
| * | | | | | retime_mode -> dff_modeEddie Hung2019-08-201-7/+7
| * | | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXMEEddie Hung2019-08-201-65/+13
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-6/+6
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-191-1/+1
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| * | | | | | | | Remove debugEddie Hung2019-08-191-1/+1
| * | | | | | | | Add (* abc_arrival *) attributeEddie Hung2019-08-191-1/+1
| * | | | | | | | Move from cell attr to module attrEddie Hung2019-08-191-24/+64
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-1920-263/+263
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| * | | | | | | | | Use attributes instead of paramsEddie Hung2019-08-191-11/+25
| * | | | | | | | | Set abc_flop and use it in toposortEddie Hung2019-08-191-31/+51
| * | | | | | | | | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1627-1267/+1501
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