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* Add v2 memory cells.Marcelina Koƛcielnicka2021-08-111-0/+1
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-5/+5
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* Clean up `passes/techmap/extract.cc`.Alberto Gonzalez2020-04-051-43/+36
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-31/+31
* ID(\\.*) -> ID(.*)Eddie Hung2019-08-151-31/+31
* Transform all "\\*" identifiers into ID()Eddie Hung2019-08-151-31/+31
* substr() -> compare()Eddie Hung2019-08-071-5/+5
* stoi -> atoiEddie Hung2019-08-071-5/+5
* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-5/+5
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added "yosys -D" featureClifford Wolf2016-04-211-5/+5
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* equiv_purge bugfix, using SigChunk in Yosys namespaceClifford Wolf2015-10-241-1/+1
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-3/+3
* Fixed trailing whitespacesClifford Wolf2015-07-021-4/+4
* Added support for "file names with blanks"Clifford Wolf2015-04-081-0/+2
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-2/+2
* More Win32 build fixesClifford Wolf2014-10-101-10/+7
* namespace YosysClifford Wolf2014-09-271-258/+259
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-4/+5
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-4/+5
* Added module->portsClifford Wolf2014-08-141-2/+2
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-2/+2
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-15/+15
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-6/+6
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-1/+1
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-291-3/+3
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-2/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-6/+6
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-3/+3
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-4/+1
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-2/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-3/+5
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-12/+12
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-12/+12
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-10/+3
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-33/+24
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-3/+3
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-1/+1
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-1/+1
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-12/+12
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-12/+12
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-201-0/+79