diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
| commit | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (patch) | |
| tree | 4bccb9f45ccad05346697c79afca9a1b21dced9c /passes/techmap/extract.cc | |
| parent | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (diff) | |
| download | yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.tar.gz yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.tar.bz2 yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.zip | |
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Diffstat (limited to 'passes/techmap/extract.cc')
| -rw-r--r-- | passes/techmap/extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 19d323341..ed389f2fb 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -296,7 +296,7 @@ namespace SigSet<std::pair<std::string, int>> sig2port; // create new cell - RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name); + RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name); // create cell ports for (auto &it : needle->wires_) { |