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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 19:09:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 19:09:45 +0200 |
| commit | 6fe48cf41ef0b0158879add600c7a426a5c4a762 (patch) | |
| tree | c9de66f5fe0848219a23492e89d3ff11bd6b63ed /passes/techmap/extract.cc | |
| parent | 2a0f577f839bc43a5045ddf5a2b580bba8cabeab (diff) | |
| download | yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.tar.gz yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.tar.bz2 yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.zip | |
equiv_purge bugfix, using SigChunk in Yosys namespace
Diffstat (limited to 'passes/techmap/extract.cc')
| -rw-r--r-- | passes/techmap/extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 68a7fc1f6..d9ec4bc6a 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -737,7 +737,7 @@ struct ExtractPass : public Pass { RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; for (auto &conn : cell->connections()) { - std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second); + std::vector<SigChunk> chunks = sigmap(conn.second); for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires_.at(chunk.wire->name); |