| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -5/+5 |
| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
| * | equiv_purge bugfix, using SigChunk in Yosys namespace | Clifford Wolf | 2015-10-24 | 1 | -1/+1 |
| * | Re-created command-reference-manual.tex, copied some doc fixes to online help | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -3/+3 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -4/+4 |
| * | Added support for "file names with blanks" | Clifford Wolf | 2015-04-08 | 1 | -0/+2 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -2/+2 |
| * | More Win32 build fixes | Clifford Wolf | 2014-10-10 | 1 | -10/+7 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -258/+259 |
| * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 1 | -4/+5 |
| * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 1 | -4/+5 |
| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -2/+2 |
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
| * | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -15/+15 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -6/+6 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
| * | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 | 1 | -3/+3 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -2/+1 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -6/+6 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -4/+1 |
| * | More RTLIL::Cell API usage cleanups | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -3/+5 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -12/+12 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -12/+12 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -10/+3 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -33/+24 |
| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -3/+3 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -12/+12 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -12/+12 |
| * | Added "extract -ignore_parameters" and "extract -ignore_param ..." | Clifford Wolf | 2014-02-20 | 1 | -0/+79 |
| * | Added "extract -map %<design_name>" | Clifford Wolf | 2014-02-20 | 1 | -10/+30 |
| * | Moved some passes to other source directories | Clifford Wolf | 2014-02-08 | 1 | -0/+680 |
