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* Added sat -show-regs, -show-public, -show-allClifford Wolf2015-08-181-0/+39
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-145-12/+12
* Added "miter -assert"Clifford Wolf2015-07-251-1/+93
* Fixed trailing whitespacesClifford Wolf2015-07-025-16/+16
* Added logic-loop error handling to freduceClifford Wolf2015-06-301-0/+11
* don't consider blackbox modules in "sat" commandClifford Wolf2015-04-181-7/+5
* Added non-std verilog assume() statementClifford Wolf2015-02-261-11/+29
* Fixed "sat -initsteps" off-by-one bugClifford Wolf2015-02-221-1/+1
* Added "sat -stepsize" and "sat -tempinduct-step"Clifford Wolf2015-02-211-21/+64
* sat docu changeClifford Wolf2015-02-211-0/+3
* When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.Clifford Wolf2015-02-211-0/+5
* Added "sat -tempinduct-baseonly -tempinduct-inductonly"Clifford Wolf2015-02-211-66/+92
* Fixed basecase init for "sat -tempinduct"Clifford Wolf2015-02-211-1/+6
* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-213-73/+74
* format fixes in "sat -dump_json"Clifford Wolf2015-02-191-18/+17
* Added "sat -dump_json" (WaveJSON format)Clifford Wolf2015-02-191-4/+92
* Improved an error messageClifford Wolf2015-01-281-1/+1
* Added "sat -show-ports"Clifford Wolf2015-01-271-2/+7
* Moved equiv stuff to passes/equiv/Clifford Wolf2015-01-224-598/+0
* Progress in equiv_simpleClifford Wolf2015-01-211-39/+105
* Added equiv_simpleClifford Wolf2015-01-192-0/+188
* Added equiv_statusClifford Wolf2015-01-192-0/+95
* Added equiv_make commandClifford Wolf2015-01-192-0/+249
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Added log_warning() APIClifford Wolf2014-11-092-3/+3
* Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-102-3/+3
* namespace YosysClifford Wolf2014-09-275-20/+28
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-012-988/+0
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-241-0/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-2/+2
* Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-091-6/+22
* Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-091-19/+0
* Fixed sharing of reduce operatorClifford Wolf2014-08-081-0/+13
* Added "sat -prove-skip"Clifford Wolf2014-08-081-2/+16
* Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-071-2/+2
* Fixed "share" for memory read portsClifford Wolf2014-08-031-0/+7
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-021-1/+1
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-3/+3
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-024-31/+31
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-311-5/+6
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-314-97/+97
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-276-21/+21
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-275-14/+14
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-275-34/+34
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