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passes
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sat
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Author
Age
Files
Lines
*
Added sat -show-regs, -show-public, -show-all
Clifford Wolf
2015-08-18
1
-0
/
+39
*
Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
1
-1
/
+1
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
5
-12
/
+12
*
Added "miter -assert"
Clifford Wolf
2015-07-25
1
-1
/
+93
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
5
-16
/
+16
*
Added logic-loop error handling to freduce
Clifford Wolf
2015-06-30
1
-0
/
+11
*
don't consider blackbox modules in "sat" command
Clifford Wolf
2015-04-18
1
-7
/
+5
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
1
-11
/
+29
*
Fixed "sat -initsteps" off-by-one bug
Clifford Wolf
2015-02-22
1
-1
/
+1
*
Added "sat -stepsize" and "sat -tempinduct-step"
Clifford Wolf
2015-02-21
1
-21
/
+64
*
sat docu change
Clifford Wolf
2015-02-21
1
-0
/
+3
*
When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
Clifford Wolf
2015-02-21
1
-0
/
+5
*
Added "sat -tempinduct-baseonly -tempinduct-inductonly"
Clifford Wolf
2015-02-21
1
-66
/
+92
*
Fixed basecase init for "sat -tempinduct"
Clifford Wolf
2015-02-21
1
-1
/
+6
*
Replaced ezDefaultSAT with ezSatPtr
Clifford Wolf
2015-02-21
3
-73
/
+74
*
format fixes in "sat -dump_json"
Clifford Wolf
2015-02-19
1
-18
/
+17
*
Added "sat -dump_json" (WaveJSON format)
Clifford Wolf
2015-02-19
1
-4
/
+92
*
Improved an error message
Clifford Wolf
2015-01-28
1
-1
/
+1
*
Added "sat -show-ports"
Clifford Wolf
2015-01-27
1
-2
/
+7
*
Moved equiv stuff to passes/equiv/
Clifford Wolf
2015-01-22
4
-598
/
+0
*
Progress in equiv_simple
Clifford Wolf
2015-01-21
1
-39
/
+105
*
Added equiv_simple
Clifford Wolf
2015-01-19
2
-0
/
+188
*
Added equiv_status
Clifford Wolf
2015-01-19
2
-0
/
+95
*
Added equiv_make command
Clifford Wolf
2015-01-19
2
-0
/
+249
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
1
-1
/
+1
*
Added log_warning() API
Clifford Wolf
2014-11-09
2
-3
/
+3
*
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
Clifford Wolf
2014-10-10
1
-1
/
+1
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
2
-3
/
+3
*
namespace Yosys
Clifford Wolf
2014-09-27
5
-20
/
+28
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
1
-1
/
+1
*
Fixes in old SAT example.ys
Clifford Wolf
2014-09-01
1
-3
/
+4
*
Moved "share" and "wreduce" to passes/opt/
Clifford Wolf
2014-09-01
2
-988
/
+0
*
azonenberg: Make dump_vcd save model when temporal induction fails due to ste...
Clifford Wolf
2014-08-24
1
-0
/
+2
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
1
-2
/
+2
*
Fixed "share" for complex scenarios with never-active cells
Clifford Wolf
2014-08-09
1
-6
/
+22
*
Do not share any $reduce_* cells (its complicated and not worth it anyways)
Clifford Wolf
2014-08-09
1
-19
/
+0
*
Fixed sharing of reduce operator
Clifford Wolf
2014-08-08
1
-0
/
+13
*
Added "sat -prove-skip"
Clifford Wolf
2014-08-08
1
-2
/
+16
*
Use "-keepdc" in "miter -equiv -flatten"
Clifford Wolf
2014-08-07
1
-2
/
+2
*
Fixed "share" for memory read ports
Clifford Wolf
2014-08-03
1
-0
/
+7
*
Removed at() method from RTLIL::IdString
Clifford Wolf
2014-08-02
1
-1
/
+1
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
1
-3
/
+3
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
4
-31
/
+31
*
Renamed modwalker.h to modtools.h
Clifford Wolf
2014-07-31
1
-5
/
+6
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
4
-97
/
+97
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
1
-1
/
+1
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
6
-21
/
+21
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
5
-14
/
+14
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
5
-34
/
+34
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