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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-30 17:11:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-30 17:11:46 +0200 |
| commit | ee9188a5b4013f22d2694d4c3e5bb7d08438bfb3 (patch) | |
| tree | a4e32f15bd722916e6b2c2dd7f1b4addaeab5fd3 /passes/sat | |
| parent | 7987f232003ea30ac9200e4ba0f5d14eae69505c (diff) | |
| download | yosys-ee9188a5b4013f22d2694d4c3e5bb7d08438bfb3.tar.gz yosys-ee9188a5b4013f22d2694d4c3e5bb7d08438bfb3.tar.bz2 yosys-ee9188a5b4013f22d2694d4c3e5bb7d08438bfb3.zip | |
Added logic-loop error handling to freduce
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/freduce.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 8a5301ec3..a60de4ee0 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -229,6 +229,7 @@ struct PerformReduction SigMap &sigmap; drivers_t &drivers; std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs; + pool<SigBit> recursion_guard; ezSatPtr ez; SatGen satgen; @@ -246,6 +247,15 @@ struct PerformReduction if (sigdepth.count(out) != 0) return sigdepth.at(out); + if (recursion_guard.count(out)) { + string loop_signals; + for (auto loop_bit : recursion_guard) + loop_signals += string(" ") + log_signal(loop_bit); + log_error("Found logic loop:%s\n", loop_signals.c_str()); + } + + recursion_guard.insert(out); + if (drivers.count(out) != 0) { std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out); if (celldone.count(drv.first) == 0) { @@ -264,6 +274,7 @@ struct PerformReduction sigdepth[out] = 0; } + recursion_guard.erase(out); return sigdepth.at(out); } |