iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1168 from whitequark/bugpoint-processes	Clifford Wolf	2019-07-09	1	-8/+24
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\| *	proc_clean: add -quiet option.	whitequark	2019-07-09	1	-8/+24
* \|	Merge pull request #1169 from whitequark/more-proc-cleanups	Clifford Wolf	2019-07-09	5	-22/+168
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\| * \|	proc_prune: promote assigns to module connections when legal.	whitequark	2019-07-09	3	-33/+42
\| * \|	proc_prune: new pass.	whitequark	2019-07-09	3	-1/+138
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* /	proc_mux: consider \src attribute on CaseRule.	whitequark	2019-07-08	1	-10/+16
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*	Improve proc full_case detection and handling, fixes #931	Clifford Wolf	2019-04-18	2	-5/+63
*	Revert #895	Eddie Hung	2019-04-16	1	-28/+0
*	Revert "Recognise default entry in case even if all cases covered (fix for #9...	Eddie Hung	2019-04-15	1	-1/+1
*	Recognise default entry in case even if all cases covered (#931)	Eddie Hung	2019-04-11	1	-1/+1
*	proc_mux: Fix crash when trying to optimize non-existant mux to shiftx	Sylvain Munaut	2019-04-03	1	-1/+1
*	Create one $shiftx per bit in width	Eddie Hung	2019-03-25	1	-10/+17
*	Add a pmux-to-shiftx optimisation to proc_mux	Eddie Hung	2019-03-23	1	-0/+21
*	proc_clean: fix critical typo.	whitequark	2019-01-23	1	-1/+1
*	proc_clean: fix fully def check to consider compare/signal length.	whitequark	2019-01-18	1	-1/+7
*	proc_clean: remove any empty cases if all cases use all-def compare.	whitequark	2018-12-23	1	-6/+28
*	proc_clean: remove any empty cases at the end of the switch.	whitequark	2018-12-22	1	-7/+3
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	8	-16/+16
*	Add warnings for driver-driver conflicts between FFs (and other cells) and co...	Clifford Wolf	2017-12-12	1	-2/+3
*	Add src attribute to extra cells generated by proc_dlatch	Clifford Wolf	2017-09-09	1	-7/+9
*	Added $global_clock verilog syntax support for creating $ff cells	Clifford Wolf	2016-10-14	1	-7/+19
*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	2	-19/+43
*	Fix all undef-muxes in dlatch input cone	Clifford Wolf	2016-06-02	1	-34/+72
*	Avoid creating undef-muxes when inferring latches in proc_dlatch	Clifford Wolf	2016-06-01	1	-0/+44
*	Fixed proc_mux performance bug	Clifford Wolf	2016-04-25	1	-0/+3
*	Fixed performance bug in proc_dlatch	Clifford Wolf	2016-04-24	1	-2/+61
*	More flexible handling of initialization values	Clifford Wolf	2016-04-22	1	-7/+22
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	8	-8/+8
*	Preserve empty $pmux default cases	Clifford Wolf	2016-03-31	1	-2/+2
*	Improved proc_mux performance for huge always blocks	Clifford Wolf	2015-12-02	1	-36/+153
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	8	-23/+23
*	Minor fixes in handling of "init" attribute	Clifford Wolf	2015-04-09	1	-0/+5
*	Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.	Clifford Wolf	2015-02-24	1	-2/+4
*	Added "proc_dlatch"	Clifford Wolf	2015-02-12	3	-1/+311
*	Removed SigSpec::extend_xx() api	Clifford Wolf	2015-01-01	1	-1/+1
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-2/+2
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	2	-2/+2
*	namespace Yosys	Clifford Wolf	2014-09-27	7	-22/+58
*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12	2	-2/+3
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	3	-81/+81
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	2	-5/+5
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	4	-11/+8
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	6	-39/+44
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	6	-6/+6
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-12/+3