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authorClifford Wolf <clifford@clifford.at>2014-12-24 09:51:17 +0100
committerClifford Wolf <clifford@clifford.at>2014-12-24 09:51:17 +0100
commitedb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 (patch)
tree602fc633af5de89d2d6d1bda480159318f4aa91d /passes/proc
parent48ca1ff9ef5bba939348ceeec75ad310afd9fcf8 (diff)
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Renamed extend() to extend_xx(), changed most users to extend_u0()
Diffstat (limited to 'passes/proc')
-rw-r--r--passes/proc/proc_arst.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index cd84cfd5b..0874d0981 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -262,7 +262,7 @@ struct ProcArstPass : public Pass {
for (auto &chunk : act.first.chunks())
if (chunk.wire && chunk.wire->attributes.count("\\init")) {
RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
- value.extend(chunk.wire->width, false);
+ value.extend_xx(chunk.wire->width, false);
arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width));
}