diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-10-10 16:59:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-10 17:07:24 +0200 |
| commit | 4569a747f8af3880e23408eb93323afc8088b78b (patch) | |
| tree | 81dcea51020173cd4951e8649f8bd8305e7c2591 /passes/proc | |
| parent | c7f5aab625bb90e766c1852592fdf42c951716c0 (diff) | |
| download | yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.gz yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.bz2 yosys-4569a747f8af3880e23408eb93323afc8088b78b.zip | |
Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 2 | ||||
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index d7cb38bcd..cd84cfd5b 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -174,7 +174,7 @@ restart_proc_arst: for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); - for (int i = 0; i < SIZE(rspec); i++) + for (int i = 0; i < GetSize(rspec); i++) if (rspec[i].wire == NULL) rval[i] = rspec[i]; RTLIL::SigSpec last_rval; diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d701f00a5..427e0d567 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = SIZE(sw->cases[i]->compare) == 0 && (!pool.empty() || SIZE(sw->signal) == 0); + bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; |