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* Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonlyDavid Shah2020-02-021-0/+7
|\ | | | | synth_xilinx: add -dsp-multonly
| * xilinx_dsp: Add multonly scratchpad var to bypassDavid Shah2020-02-011-0/+7
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
| | | | | | | | Just like Verilog...
* | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-241-3/+12
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* xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-171-1/+1
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* ice40_dsp: fix typoEddie Hung2020-01-171-2/+2
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* ConsistencyEddie Hung2020-01-172-4/+6
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* xilinx_dsp: add parameter defaultsEddie Hung2020-01-171-7/+7
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* ice40_dsp: add default values for parametersEddie Hung2020-01-172-11/+11
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* ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputsEddie Hung2020-01-171-0/+5
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* fixed invalid charMiodrag Milanovic2019-12-251-1/+1
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* Minor nit fixesMarcin Kościelnicki2019-12-251-2/+2
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* Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG tooEddie Hung2019-12-231-8/+18
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* Fix CEA/CEB checkEddie Hung2019-12-231-2/+2
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* Fix checking CE[AB] and for direct connectionsEddie Hung2019-12-231-18/+40
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* Support unregistered cascades for A and B inputsEddie Hung2019-12-231-47/+74
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* Add DSP48A* PCOUT -> PCIN cascade supportEddie Hung2019-12-231-10/+10
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* xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-224-11/+886
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* ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
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* -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
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* Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-7/+11
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* ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-17/+55
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* Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-0/+8
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* Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
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* ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
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* Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
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* Fix #1462, #1480.Marcin Kościelnicki2019-11-192-9/+11
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* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
| | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* Fix dffmux peepopt init handlingClifford Wolf2019-10-162-27/+113
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move GENERATE_PATTERN macro to separate utility headerClifford Wolf2019-10-163-128/+157
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Disable left-over log_debug in peepopt_dffmux.pmgClifford Wolf2019-10-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-081-47/+81
|\ | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming
| * Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-021-23/+26
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| * Refactor peepopt_dffmux and be sensitive to \init when trimmingEddie Hung2019-10-021-32/+63
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* | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-084-68/+356
|\ \ | | | | | | Add notes and comments for xilinx_dsp
| * | Missed thisEddie Hung2019-10-051-3/+4
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| * | Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
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| * | Add note on pattern detectorEddie Hung2019-10-051-3/+7
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| * | Add comments for xilinx_dsp_cascadeEddie Hung2019-10-041-12/+100
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| * | Improve comments for xilinx_dsp_CREGEddie Hung2019-10-041-6/+7
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| * | Fix commentEddie Hung2019-10-041-1/+1
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| * | Restore optimisation for sigM.empty()Eddie Hung2019-10-041-1/+4
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| * | Retry on fixing TODOsEddie Hung2019-10-042-13/+1
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| * | Revert "Fix TODOs"Eddie Hung2019-10-042-0/+20
| | | | | | | | | | | | This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
| * | More comments, cleanupEddie Hung2019-10-042-41/+108
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| * | Fix TODOsEddie Hung2019-10-042-20/+0
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| * | ConsistencyEddie Hung2019-10-041-3/+3
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| * | Add comments for xilinx_dspEddie Hung2019-10-043-6/+134
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* | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarryClifford Wolf2019-10-061-0/+4
|\ \ \ | | | | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
| * | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-051-0/+4
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