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path: root/passes/pmgen/xilinx_srl.pmg
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* Use new port/param overload in pmgEddie Hung2019-09-201-15/+15
* Account for D port being a constantEddie Hung2019-08-281-4/+4
* More cleanupEddie Hung2019-08-281-12/+14
* Do not use default_params dict, hardcode default values, cleanupEddie Hung2019-08-281-9/+8
* Always generate if no matchEddie Hung2019-08-281-1/+1
* Improve xilinx_srl.fixed generate, add .variable generateEddie Hung2019-08-261-26/+75
* Populate generate for xilinx_srl.fixed patternEddie Hung2019-08-261-22/+54
* Do not allow Q of last cell of variable length SRL to be (* keep *)Eddie Hung2019-08-231-0/+1
* Also add first.Q to chain_bits since variable lengthEddie Hung2019-08-231-0/+1
* Do not enforce !EN_POLARITY on $dffeEddie Hung2019-08-231-2/+0
* Cleanup FDRE matchingEddie Hung2019-08-231-45/+19
* Oops don't need a finally blockEddie Hung2019-08-231-5/+0
* Keep track of bits in variable length chain, to check for tapsEddie Hung2019-08-231-0/+12
* Don't forget $dff has no ENEddie Hung2019-08-231-2/+4
* Same for variable lengthEddie Hung2019-08-231-2/+10
* Filter on en_port for fixed lengthEddie Hung2019-08-231-4/+24
* Check clock is consistentEddie Hung2019-08-231-5/+25
* Check for non unique nusers/fanoutsEddie Hung2019-08-231-2/+2
* Cope with possibility that D could connect to Q on same cellEddie Hung2019-08-231-1/+1
* xilinx_srl to use 'slice' features of pmgen for word levelEddie Hung2019-08-231-16/+18
* Remove output_bitsEddie Hung2019-08-221-4/+6
* Reuse varEddie Hung2019-08-211-1/+1
* Revert "Trim shiftx_width when upper bits are 1'bx"Eddie Hung2019-08-211-6/+1
* Trim shiftx_width when upper bits are 1'bxEddie Hung2019-08-211-1/+6
* Add variable length support to xilinx_srlEddie Hung2019-08-211-2/+64
* Rename pattern to fixedEddie Hung2019-08-211-1/+1
* attribute -> attrEddie Hung2019-08-211-4/+4
* Use Cell::has_keep_attribute()Eddie Hung2019-08-211-4/+4
* xilinx_srl to support FDRE and FDRE_1Eddie Hung2019-08-211-4/+50
* Reject if not minlen from inside pattern matcherEddie Hung2019-08-211-1/+2
* Get wire via SigBitEddie Hung2019-08-211-4/+4
* Respect \keep on cells or wiresEddie Hung2019-08-211-2/+10
* Initial progress on xilinx_srlEddie Hung2019-08-211-0/+92