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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 19:18:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 19:18:27 -0700 |
| commit | 5c8344363f6405d1d6e21868b10b6dc9e02148a4 (patch) | |
| tree | 5639e8f958fa95fafb41a46f65bc1e2fd7ccdc50 /passes/pmgen/xilinx_srl.pmg | |
| parent | c7859531c2cf56df67a0767a6333ecf9acab7251 (diff) | |
| download | yosys-5c8344363f6405d1d6e21868b10b6dc9e02148a4.tar.gz yosys-5c8344363f6405d1d6e21868b10b6dc9e02148a4.tar.bz2 yosys-5c8344363f6405d1d6e21868b10b6dc9e02148a4.zip | |
Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.
Diffstat (limited to 'passes/pmgen/xilinx_srl.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index d3ba0109f..3f4efebe9 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -164,11 +164,6 @@ endmatch code shiftx_width shiftx_width = param(shiftx, \A_WIDTH).as_int(); - while (shiftx_width > 1) { - if (port(shiftx, \A)[shiftx_width-1] != State::Sx) - break; - --shiftx_width; - } endcode match first @@ -182,7 +177,7 @@ code chain.push_back(first); subpattern(tail); finally - if (GetSize(chain) == shiftx_width) + if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int()) accept; chain.clear(); endcode |