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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:54:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:54:56 -0700 |
| commit | c3e9627afeb6b69f244983f2f23fb5473e61ab19 (patch) | |
| tree | 1c4ee1a0c2fe61b8aedb139c38510988cdb04b57 /passes/pmgen/xilinx_srl.pmg | |
| parent | 0ebe2c9831591d4f969139c5ec0776911284a954 (diff) | |
| download | yosys-c3e9627afeb6b69f244983f2f23fb5473e61ab19.tar.gz yosys-c3e9627afeb6b69f244983f2f23fb5473e61ab19.tar.bz2 yosys-c3e9627afeb6b69f244983f2f23fb5473e61ab19.zip | |
Always generate if no match
Diffstat (limited to 'passes/pmgen/xilinx_srl.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index e8288c54a..bdb59c2f7 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -142,7 +142,7 @@ match next filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) -generate 10 +generate Cell *cell = module->addCell(NEW_ID, chain.back()->type); cell->setPort(\C, chain.back()->getPort(\C)); cell->setPort(\D, module->addWire(NEW_ID)); |