iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Use new port/param overload in pmg	Eddie Hung	2019-09-20	1	-15/+15
*	Account for D port being a constant	Eddie Hung	2019-08-28	1	-4/+4
*	More cleanup	Eddie Hung	2019-08-28	1	-12/+14
*	Do not use default_params dict, hardcode default values, cleanup	Eddie Hung	2019-08-28	1	-9/+8
*	Always generate if no match	Eddie Hung	2019-08-28	1	-1/+1
*	Improve xilinx_srl.fixed generate, add .variable generate	Eddie Hung	2019-08-26	1	-26/+75
*	Populate generate for xilinx_srl.fixed pattern	Eddie Hung	2019-08-26	1	-22/+54
*	Do not allow Q of last cell of variable length SRL to be (* keep *)	Eddie Hung	2019-08-23	1	-0/+1
*	Also add first.Q to chain_bits since variable length	Eddie Hung	2019-08-23	1	-0/+1
*	Do not enforce !EN_POLARITY on $dffe	Eddie Hung	2019-08-23	1	-2/+0
*	Cleanup FDRE matching	Eddie Hung	2019-08-23	1	-45/+19
*	Oops don't need a finally block	Eddie Hung	2019-08-23	1	-5/+0
*	Keep track of bits in variable length chain, to check for taps	Eddie Hung	2019-08-23	1	-0/+12
*	Don't forget $dff has no EN	Eddie Hung	2019-08-23	1	-2/+4
*	Same for variable length	Eddie Hung	2019-08-23	1	-2/+10
*	Filter on en_port for fixed length	Eddie Hung	2019-08-23	1	-4/+24
*	Check clock is consistent	Eddie Hung	2019-08-23	1	-5/+25
*	Check for non unique nusers/fanouts	Eddie Hung	2019-08-23	1	-2/+2
*	Cope with possibility that D could connect to Q on same cell	Eddie Hung	2019-08-23	1	-1/+1
*	xilinx_srl to use 'slice' features of pmgen for word level	Eddie Hung	2019-08-23	1	-16/+18
*	Remove output_bits	Eddie Hung	2019-08-22	1	-4/+6
*	Reuse var	Eddie Hung	2019-08-21	1	-1/+1
*	Revert "Trim shiftx_width when upper bits are 1'bx"	Eddie Hung	2019-08-21	1	-6/+1
*	Trim shiftx_width when upper bits are 1'bx	Eddie Hung	2019-08-21	1	-1/+6
*	Add variable length support to xilinx_srl	Eddie Hung	2019-08-21	1	-2/+64
*	Rename pattern to fixed	Eddie Hung	2019-08-21	1	-1/+1
*	attribute -> attr	Eddie Hung	2019-08-21	1	-4/+4
*	Use Cell::has_keep_attribute()	Eddie Hung	2019-08-21	1	-4/+4
*	xilinx_srl to support FDRE and FDRE_1	Eddie Hung	2019-08-21	1	-4/+50
*	Reject if not minlen from inside pattern matcher	Eddie Hung	2019-08-21	1	-1/+2
*	Get wire via SigBit	Eddie Hung	2019-08-21	1	-4/+4
*	Respect \keep on cells or wires	Eddie Hung	2019-08-21	1	-2/+10
*	Initial progress on xilinx_srl	Eddie Hung	2019-08-21	1	-0/+92