iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth_xilinx: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	1	-101/+24
*	xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only	Eddie Hung	2020-04-22	1	-1/+1
*	Cleanup use of hard-coded default parameters in light of #1945	Eddie Hung	2020-04-22	1	-12/+12
*	Minor nit fixes	Marcin Kościelnicki	2019-12-25	1	-2/+2
*	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	Eddie Hung	2019-12-23	1	-8/+18
*	Fix CEA/CEB check	Eddie Hung	2019-12-23	1	-2/+2
*	Fix checking CE[AB] and for direct connections	Eddie Hung	2019-12-23	1	-18/+40
*	Support unregistered cascades for A and B inputs	Eddie Hung	2019-12-23	1	-47/+74
*	Add DSP48A* PCOUT -> PCIN cascade support	Eddie Hung	2019-12-23	1	-10/+10
*	Add comment on why we have to match for clock-enable/reset muxes	Eddie Hung	2019-10-05	1	-1/+4
*	Add comments for xilinx_dsp_cascade	Eddie Hung	2019-10-04	1	-12/+100
*	Ooops AREG and BREG to default to -1	Eddie Hung	2019-09-27	1	-2/+2
*	Do not always zero out C (e.g. during cascade breaks)	Eddie Hung	2019-09-26	1	-5/+3
*	Zero out ports	Eddie Hung	2019-09-26	1	-2/+2
*	xilinx_dsp_cascade to also cascade AREG and BREG	Eddie Hung	2019-09-26	1	-431/+153
*	Try recursive pmgen for P cascade	Eddie Hung	2019-09-26	1	-88/+118
*	Move unextend initialisation later	Eddie Hung	2019-09-23	1	-12/+9
*	OPMODE is port not param	Eddie Hung	2019-09-20	1	-7/+6
*	WIP for xiinx_dsp_cascadeAB	Eddie Hung	2019-09-20	1	-3/+499
*	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	Eddie Hung	2019-09-20	1	-0/+94