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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-23 14:22:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-23 14:22:13 -0800 |
| commit | 75acaff6f5416137fdf515bda5c214ccc228df98 (patch) | |
| tree | ea6d4234c4c5739424af35f60a477bc8b41e0f00 /passes/pmgen/xilinx_dsp_cascade.pmg | |
| parent | edabe73377e08ebdc1315d9a907f0a4ff8bfddd3 (diff) | |
| download | yosys-75acaff6f5416137fdf515bda5c214ccc228df98.tar.gz yosys-75acaff6f5416137fdf515bda5c214ccc228df98.tar.bz2 yosys-75acaff6f5416137fdf515bda5c214ccc228df98.zip | |
Fix CEA/CEB check
Diffstat (limited to 'passes/pmgen/xilinx_dsp_cascade.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_cascade.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 1116afd41..9fdefff31 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -257,7 +257,7 @@ code argQ clock AREG else if (param(prev, \AREG, 2) == 2) CEA = \CEA1; else log_abort(); - if (!dffcemux && port(prev, CEA, State::S0) != State::S0) + if (!dffcemux && port(prev, CEA, State::S0) != State::S1) goto reject_AREG; if (dffcemux && port(dffcemux, \S) != port(prev, CEA, State::S0)) goto reject_AREG; @@ -303,7 +303,7 @@ code argQ clock BREG else log_abort(); } else log_abort(); - if (!dffcemux && port(prev, CEB, State::S0) != State::S0) + if (!dffcemux && port(prev, CEB, State::S0) != State::S1) goto reject_BREG; if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0)) goto reject_BREG; |