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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 13:40:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 13:40:38 -0700 |
| commit | 58f31096abbb0bc68c8339c88b7db410b8edcdba (patch) | |
| tree | e9f98c371a8992f48c2a87f19892d7cdf8fbf605 /passes/pmgen/xilinx_dsp_cascade.pmg | |
| parent | af59856ba1be1f7cde3154994334f45500af6c22 (diff) | |
| download | yosys-58f31096abbb0bc68c8339c88b7db410b8edcdba.tar.gz yosys-58f31096abbb0bc68c8339c88b7db410b8edcdba.tar.bz2 yosys-58f31096abbb0bc68c8339c88b7db410b8edcdba.zip | |
Zero out ports
Diffstat (limited to 'passes/pmgen/xilinx_dsp_cascade.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_cascade.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 2fc943a66..d4b4b8e22 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -67,7 +67,7 @@ finally Wire *cascade = module->addWire(NEW_ID, 30); dsp_pcin->setPort(ID(ACIN), cascade); dsp->setPort(ID(ACOUT), cascade); - dsp_pcin->unsetPort(ID(A)); + dsp_pcin->setPort(ID(A), Const(0, 30)); add_siguser(cascade, dsp_pcin); add_siguser(cascade, dsp); @@ -80,7 +80,7 @@ finally Wire *cascade = module->addWire(NEW_ID, 18); dsp_pcin->setPort(ID(BCIN), cascade); dsp->setPort(ID(BCOUT), cascade); - dsp_pcin->unsetPort(ID(B)); + dsp_pcin->setPort(ID(B), Const(0, 18)); add_siguser(cascade, dsp_pcin); add_siguser(cascade, dsp); |