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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* Added wreduce $mul support and fixed signed $mul opt_const bugClifford Wolf2015-09-251-4/+36
* Added detection of "mux inverter" chains in opt_constClifford Wolf2015-09-181-0/+2
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* Added opt_const -clkinvClifford Wolf2015-07-011-3/+88
* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-291-0/+19
* Using design->selected_modules() in opt_*Clifford Wolf2015-02-031-1/+1
* Bugfix in opt_const $eq -> buffer codeClifford Wolf2015-01-311-4/+4
* Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)Clifford Wolf2015-01-131-5/+0
* disabled problematic mux -> and/or transformClifford Wolf2015-01-071-2/+7
* dict<> ref vs insert bugfixClifford Wolf2015-01-061-10/+13
* Renamed hashmap.h to hashlib.h, some related improvementsClifford Wolf2014-12-281-1/+1
* More hashtable finetuningClifford Wolf2014-12-271-1/+1
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-1/+1
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-3/+3
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-3/+3
* Improved TopoSort determinismClifford Wolf2014-11-071-1/+1
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-311-3/+13
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-14/+14
* namespace YosysClifford Wolf2014-09-271-5/+9
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
* Removed $bu0 cell typeClifford Wolf2014-09-041-6/+4
* Added design->scratchpadClifford Wolf2014-08-301-17/+3
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
* Renamed toposort.h to utils.hClifford Wolf2014-08-171-1/+1
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-6/+6
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-21/+21
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-98/+98
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-7/+9
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-2/+1
* Improved performance of opt_const on large modulesClifford Wolf2014-07-271-29/+54
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-271-10/+10
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-1/+1
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-2/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-17/+19
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-101/+101
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-101/+101
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-2/+1
* Added cover() calls to opt_constClifford Wolf2014-07-241-9/+45
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-2/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-8/+6
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-7/+2
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-46/+46
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-46/+46
* Added "opt_const -keepdc"Clifford Wolf2014-07-211-12/+158
* Added mul to mux conversion to "opt_const -fine"Clifford Wolf2014-07-211-0/+55