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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-26 21:35:22 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-26 21:35:22 +0100 |
| commit | 9e6fb0b02ccf209528ead026de8eef0a8a0d7740 (patch) | |
| tree | f3e7c1c9babc232a806b92a625bc447b1b75c7c4 /passes/opt/opt_const.cc | |
| parent | e52d1f9b9a7f71634d4e8e8228060f792fa20dec (diff) | |
| download | yosys-9e6fb0b02ccf209528ead026de8eef0a8a0d7740.tar.gz yosys-9e6fb0b02ccf209528ead026de8eef0a8a0d7740.tar.bz2 yosys-9e6fb0b02ccf209528ead026de8eef0a8a0d7740.zip | |
Replaced std::unordered_map as implementation for Yosys::dict
Diffstat (limited to 'passes/opt/opt_const.cc')
| -rw-r--r-- | passes/opt/opt_const.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 7f800bde9..9c1a18782 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -199,7 +199,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map; TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells; - dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit; + dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_ptr_ops> cell_to_inbit; dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell; for (auto cell : module->cells()) |