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author | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
commit | 8927aa6148f5575b2da9bfb76afb4af076fe18f3 (patch) | |
tree | 4da0980333589d4785880e48383c6f44e4a94887 /passes/opt/opt_const.cc | |
parent | b9cb483f3e2a498ee75a422e09164a920918362b (diff) | |
download | yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.tar.gz yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.tar.bz2 yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.zip |
Removed $bu0 cell type
Diffstat (limited to 'passes/opt/opt_const.cc')
-rw-r--r-- | passes/opt/opt_const.cc | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ad6961872..d315dba35 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -181,7 +181,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com log("\n"); } - cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); + cover_list("opt.opt_const.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); did_something = true; @@ -236,7 +236,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (do_fine) { - if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || + if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map)) goto next_cell; @@ -586,7 +586,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (!keepdc) { - bool identity_bu0 = false; bool identity_wrt_a = false; bool identity_wrt_b = false; @@ -607,7 +606,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (b.is_fully_const() && b.as_bool() == false) - identity_wrt_a = true, identity_bu0 = true; + identity_wrt_a = true; } if (cell->type == "$mul") @@ -646,7 +645,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } - cell->type = identity_bu0 ? "$bu0" : "$pos"; + cell->type = "$pos"; cell->unsetPort("\\B"); cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); @@ -840,7 +839,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo FOLD_2ARG_CELL(pow) FOLD_1ARG_CELL(pos) - FOLD_1ARG_CELL(bu0) FOLD_1ARG_CELL(neg) // be very conservative with optimizing $mux cells as we do not want to break mux trees |