iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Progress in memory_bram	Clifford Wolf	2015-01-01	1	-37/+145
*	Progress in memory_bram	Clifford Wolf	2014-12-31	1	-7/+115
*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31	2	-0/+286
*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-2/+2
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-12/+12
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-5/+5
*	namespace Yosys	Clifford Wolf	2014-09-27	6	-12/+32
*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16	1	-4/+6
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30	1	-16/+28
*	Using worker class in memory_map	Clifford Wolf	2014-08-30	1	-226/+231
*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	3	-9/+9
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-3/+2
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	1	-5/+6
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	5	-128/+128
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	4	-4/+4
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-0/+2
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	4	-15/+11
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-15/+11
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	5	-5/+5
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	5	-9/+9
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-2/+2
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-46/+16
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-17/+29
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	5	-128/+128
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	5	-128/+128
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	4	-59/+20
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-5/+5
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	3	-10/+0
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+4
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	4	-32/+32
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	4	-32/+32
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-2/+2
*	Improved memory_share log messages	Clifford Wolf	2014-07-19	1	-3/+3
*	More verbose memory_share help message	Clifford Wolf	2014-07-19	1	-0/+17
*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19	1	-0/+180
*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19	1	-4/+12
*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18	2	-10/+240
*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18	1	-4/+47
*	Added memory_share	Clifford Wolf	2014-07-18	3	-0/+266
*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16	3	-38/+56
*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01	1	-0/+2
*	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08	1	-0/+1
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	4	-64/+84
*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02	1	-15/+18