diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-06-01 11:32:27 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-01 11:32:27 +0200 |
| commit | 68c99bf7349cf56385ee803144dd7d8e219be8d5 (patch) | |
| tree | 8e4fa757b9b431d71d06efac78d8337b8e6c2f27 /passes/memory | |
| parent | d5497f770bf49b893c8a90879d325a73f4d13ee5 (diff) | |
| download | yosys-68c99bf7349cf56385ee803144dd7d8e219be8d5.tar.gz yosys-68c99bf7349cf56385ee803144dd7d8e219be8d5.tar.bz2 yosys-68c99bf7349cf56385ee803144dd7d8e219be8d5.zip | |
Fixed log messages in memory_dff
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_dff.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 2502a8b61..e8da6d642 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -111,6 +111,8 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); } + + log("no (compatible) $dff found.\n"); } static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) |