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author | Clifford Wolf <clifford@clifford.at> | 2014-07-19 15:32:14 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-19 15:32:14 +0200 |
commit | 26f982ac0b69deb3cb9eda69e5cf687a69de4606 (patch) | |
tree | f2db23057b52adc3cb869a195cd2a1e86d23aa59 /passes/memory | |
parent | e441f07d895a673c0bf40dcdc76781b50834fe44 (diff) | |
download | yosys-26f982ac0b69deb3cb9eda69e5cf687a69de4606.tar.gz yosys-26f982ac0b69deb3cb9eda69e5cf687a69de4606.tar.bz2 yosys-26f982ac0b69deb3cb9eda69e5cf687a69de4606.zip |
Fixed bug in memory_share feedback-to-en code
Diffstat (limited to 'passes/memory')
-rw-r--r-- | passes/memory/memory_share.cc | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index e2fa168c3..4af0ebdca 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -120,7 +120,7 @@ struct MemoryShareWorker void translate_rd_feedback_to_en(std::string memid, std::vector<RTLIL::Cell*> &rd_ports, std::vector<RTLIL::Cell*> &wr_ports) { - std::vector<std::set<RTLIL::SigBit>> async_rd_bits; + std::map<RTLIL::SigSpec, std::vector<std::set<RTLIL::SigBit>>> async_rd_bits; std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map; std::set<RTLIL::SigBit> non_feedback_nets; @@ -187,15 +187,16 @@ struct MemoryShareWorker if (cell->parameters.at("\\CLK_ENABLE").as_bool()) continue; + RTLIL::SigSpec sig_addr = sigmap(cell->connections.at("\\ADDR")); std::vector<RTLIL::SigBit> sig_data = sigmap(cell->connections.at("\\DATA")); for (int i = 0; i < int(sig_data.size()); i++) if (non_feedback_nets.count(sig_data[i])) goto not_pure_feedback_port; - async_rd_bits.resize(std::max(async_rd_bits.size(), sig_data.size())); + async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size())); for (int i = 0; i < int(sig_data.size()); i++) - async_rd_bits[i].insert(sig_data[i]); + async_rd_bits[sig_addr][i].insert(sig_data[i]); not_pure_feedback_port:; } @@ -207,6 +208,10 @@ struct MemoryShareWorker for (auto cell : wr_ports) { + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections.at("\\ADDR")); + if (!async_rd_bits.count(sig_addr)) + continue; + log(" Analyzing write port %s.\n", log_id(cell)); std::vector<RTLIL::SigBit> cell_data = cell->connections.at("\\DATA"); @@ -224,7 +229,7 @@ struct MemoryShareWorker conditions.insert(state); } - find_data_feedback(async_rd_bits.at(i), cell_data[i], state, conditions); + find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions); cell_en[i] = conditions_to_logic(conditions, created_conditions); } @@ -333,6 +338,9 @@ struct MemoryShareWorker void consolidate_wr_by_addr(std::string memid, std::vector<RTLIL::Cell*> &wr_ports) { + if (wr_ports.size() <= 1) + return; + log("Consolidating write ports of memory %s by address:\n", log_id(memid)); std::map<RTLIL::SigSpec, int> last_port_by_addr; |