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author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
commit | 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch) | |
tree | 9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /passes/memory | |
parent | 7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff) | |
download | yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.gz yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.bz2 yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.zip |
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'passes/memory')
-rw-r--r-- | passes/memory/memory_dff.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 8bae24cff..dee48597f 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI for (size_t i = 0; i < sig.chunks().size(); i++) { - RTLIL::SigChunk &chunk = sig.chunks()[i]; + RTLIL::SigChunk &chunk = sig.chunks_rw()[i]; if (chunk.wire == NULL) continue; |