| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | memory_dff: Fix needlessly duplicating enable bits. | Marcelina Kościelnicka | 2020-10-22 | 1 | -0/+8 | |
| | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409. | |||||
| * | memory_bram: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -121/+90 | |
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| * | memory_map: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -138/+81 | |
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| * | memory_unpack: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -106/+10 | |
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| * | memory_collect: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -223/+9 | |
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| * | memory_nordff: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -63/+9 | |
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| * | memory_dff: Refactor to use FfInitVals. | Marcelina Kościelnicka | 2020-07-24 | 1 | -12/+5 | |
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| * | memory_dff: recognize more dff cells | Marcelina Kościelnicka | 2020-07-23 | 1 | -11/+112 | |
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| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 9 | -18/+18 | |
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| * | Add flooring division operator | Xiretza | 2020-05-28 | 1 | -0/+1 | |
| | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. | |||||
| * | Add flooring modulo operator | Xiretza | 2020-05-28 | 1 | -0/+1 | |
| | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. | |||||
| * | memory_bram: Fix ignorance of valid, matched rules | David Shah | 2020-04-10 | 1 | -3/+3 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Merge pull request #1603 from whitequark/ice40-ram_style | whitequark | 2020-04-10 | 2 | -13/+148 | |
| |\ | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes | |||||
| | * | memory_map: add -attr option, to respect inference attributes. | whitequark | 2020-04-03 | 1 | -6/+113 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, memory_map (which is always a part of a synth script) would always pick up any $mem cell that was not processed by a preceding pass and lower it down to $dff/$mux cells. This is undesirable for two reasons: * If there is an explicit inference attribute set on a $mem cell, e.g. (* ram_block *), then it is arguably incorrect to map such a memory to $dff/$mux cells. * If memory_map tries to lower a memory that was intended to be mapped to a large BRAM, it often takes extraordinarily long time to finish, produces an extremely large log file, and outputs an unusable design. After this commit, properly invoked memory_map will not map any memory that has an explicit inference attribute specified, solving the first issue, and alleviating the second. The default behavior is not changed. | |||||
| | * | memory_bram: add `attr_icase` option. | whitequark | 2020-02-06 | 1 | -7/+35 | |
| | | | | | | | | | | | Some vendor toolchains use case insensitive matching for values of attributes that control BRAM inference. | |||||
| * | | Merge pull request #1890 from boqwxp/cleanup_memory_collect | N. Engelhardt | 2020-04-09 | 1 | -6/+3 | |
| |\ \ | | | | | | | Clean up `passes/memory/memory_collect.cc`. | |||||
| | * | | Clean up `passes/memory/memory_collect.cc`. | Alberto Gonzalez | 2020-04-09 | 1 | -6/+3 | |
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| * | | | Clean up `passes/memory/memory_unpack.cc`. | Alberto Gonzalez | 2020-04-09 | 1 | -7/+6 | |
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| * | | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 8 | -322/+322 | |
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| * | | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 3 | -40/+40 | |
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| * | | Merge pull request #1845 from YosysHQ/eddie/kernel_speedup | Eddie Hung | 2020-04-02 | 1 | -8/+8 | |
| |\ \ | | | | | | | kernel: speedup by using more pass-by-const-ref | |||||
| | * | | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 1 | -8/+8 | |
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| * | | memory_share: fix stray brace | Eddie Hung | 2020-03-30 | 1 | -1/+0 | |
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| * | | Code review fixes | Eddie Hung | 2020-03-30 | 1 | -2/+2 | |
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| * | | Apply suggestions from code review | Eddie Hung | 2020-03-30 | 1 | -4/+1 | |
| | | | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> | |||||
| * | | kernel: share a single CellTypes within a pass | Eddie Hung | 2020-03-18 | 1 | -4/+16 | |
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| * | Cleanup | Eddie Hung | 2019-12-17 | 1 | -11/+7 | |
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| * | Enforce non-existence | Eddie Hung | 2019-12-16 | 1 | -0/+4 | |
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| * | Update doc | Eddie Hung | 2019-12-16 | 1 | -4/+6 | |
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| * | More sloppiness, thanks @dh73 for spotting | Eddie Hung | 2019-12-16 | 1 | -4/+4 | |
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| * | Oops | Eddie Hung | 2019-12-16 | 1 | -4/+1 | |
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| * | Implement 'attributes' grammar | Eddie Hung | 2019-12-16 | 1 | -80/+88 | |
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| * | Fixing compiler warning/issues. Moving test script to the correct place | Diego H | 2019-12-16 | 1 | -8/+8 | |
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| * | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -68/+80 | |
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| * | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+77 | |
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| * | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 | |
| |\ | | | | | memory_collect: Copy attr from RTLIL::Memory to cell | |||||
| | * | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Add "opt_mem" pass | Clifford Wolf | 2019-11-22 | 1 | -0/+2 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -4/+4 | |
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| * | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 1 | -4/+4 | |
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| * | Use State::S{0,1} | Eddie Hung | 2019-08-06 | 2 | -6/+6 | |
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| * | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 2 | -4/+4 | |
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| * | Error out if enable > dbits | Eddie Hung | 2019-07-13 | 1 | -0/+4 | |
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| * | memory_dff: Fix checking of feedback mux input when more than one mux | David Shah | 2019-07-02 | 1 | -3/+5 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Fix spacing | Eddie Hung | 2019-06-25 | 1 | -4/+3 | |
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| * | Move only one consumer check outside of while loop | Eddie Hung | 2019-06-25 | 1 | -6/+5 | |
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| * | Walk through as many muxes as exist for rd_en | Eddie Hung | 2019-06-24 | 1 | -8/+16 | |
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| * | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | memory_bram: Consider read enable for address expansion register | David Shah | 2019-04-02 | 1 | -0/+2 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | memory_bram: Reset make_transp when growing read ports | David Shah | 2019-03-27 | 1 | -0/+1 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
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index : iCE40/yosys | |
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