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authorMarcelina Koƛcielnicka <mwk@0x04.net>2020-10-22 10:37:44 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2020-10-22 13:03:42 +0200
commiteb76d35e8030f4befb596fee6d7682d39628dc69 (patch)
tree14fd7825e5eabf1e21b40c0d57b886596dbf54c6 /passes/memory
parent1a7a597e0720f66b59b896f8e7d537dee8e37744 (diff)
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memory_dff: Fix needlessly duplicating enable bits.
When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory_dff.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 68023fd11..4adcb462e 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -46,8 +46,15 @@ struct MemoryDffWorker
{
sigmap.apply(sig);
+ dict<SigBit, SigBit> cache;
+
for (auto &bit : sig)
{
+ if (cache.count(bit)) {
+ bit = cache[bit];
+ continue;
+ }
+
if (bit.wire == NULL)
continue;
@@ -103,6 +110,7 @@ struct MemoryDffWorker
d = module->Mux(NEW_ID, rbit, d, cell->getPort(ID::SRST));
}
+ cache[bit] = d;
bit = d;
clk = this_clk;
clk_polarity = this_clk_polarity;