iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16	1	-4/+6
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*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
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*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30	1	-16/+28
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*	Using worker class in memory_map	Clifford Wolf	2014-08-30	1	-226/+231
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*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	3	-9/+9
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-3/+2
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*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	1	-5/+6
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	5	-128/+128
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	4	-4/+4
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-0/+2
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	4	-15/+11
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-15/+11
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	5	-5/+5
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	5	-9/+9
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-2/+2
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-46/+16
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-17/+29
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	5	-128/+128
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	5	-128/+128
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	4	-59/+20
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-5/+5
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	3	-10/+0
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+4
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-1/+1
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	4	-32/+32
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	4	-32/+32
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-2/+2
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*	Improved memory_share log messages	Clifford Wolf	2014-07-19	1	-3/+3
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*	More verbose memory_share help message	Clifford Wolf	2014-07-19	1	-0/+17
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*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19	1	-0/+180
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*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19	1	-4/+12
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*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18	2	-10/+240
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*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18	1	-4/+47
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*	Added memory_share	Clifford Wolf	2014-07-18	3	-0/+266
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*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16	3	-38/+56
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*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01	1	-0/+2
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*	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08	1	-0/+1
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	4	-64/+84
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*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02	1	-15/+18
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*	Added automatic memid generation to memory_unpack command	Clifford Wolf	2014-01-17	1	-2/+2
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*	Added memory_unpack command	Clifford Wolf	2014-01-17	2	-0/+117
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*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-2/+19
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	2	-3/+3
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*	A fix in memory_dff for write ports with static addresses	Clifford Wolf	2013-12-01	1	-10/+10
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*	Fixed help message typo (memory pass)	Clifford Wolf	2013-10-30	1	-1/+1
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*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17	1	-2/+7
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