aboutsummaryrefslogtreecommitdiffstats
path: root/passes/memory/memory_map.cc
Commit message (Expand)AuthorAgeFilesLines
* Use State::S{0,1}Eddie Hung2019-08-061-1/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Added read-enable to memory modelClifford Wolf2015-09-251-12/+21
* Fixed trailing whitespacesClifford Wolf2015-07-021-4/+4
* Avoid parameter values with size 0 ($mem cells)Clifford Wolf2015-04-051-1/+6
* Various fixes for memories with offsetsClifford Wolf2015-02-141-2/+9
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-2/+9
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-5/+5
* namespace YosysClifford Wolf2014-09-271-0/+4
* Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
* Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-2/+2
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-35/+35
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-39/+14
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-37/+37
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-37/+37
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-33/+9
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-4/+4
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-4/+4
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-161-35/+53
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-34/+37
* Only generate write-enable $and if WE is not constant 1 in memory_mapClifford Wolf2014-02-021-15/+18
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-1/+1
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-171-2/+7
* Added help messages to memory_* passesClifford Wolf2013-03-011-4/+15
* initial importClifford Wolf2013-01-051-0/+334