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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
| commit | 0bc95f1e049afc35bb5ea30663b0a5725dfbf584 (patch) | |
| tree | 3a8641d3a9bb5794a24145ce368f3db7a3963709 /passes/memory/memory_map.cc | |
| parent | 1565d1af69f552b790aa43fd6be194ee59ab76f3 (diff) | |
| download | yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.gz yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.bz2 yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.zip | |
Added "yosys -D" feature
Diffstat (limited to 'passes/memory/memory_map.cc')
| -rw-r--r-- | passes/memory/memory_map.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 0b8ccb363..bffeec857 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -363,7 +363,7 @@ struct MemoryMapPass : public Pass { log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); + log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); for (auto mod : design->selected_modules()) MemoryMapWorker(design, mod); |