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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:14:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:14:05 +0100 |
| commit | 93a70959f3f67ffcee8159b18a5f68904e32a074 (patch) | |
| tree | 1bf68c1a36c3d126fdb396b0ea9c06bcdc2040fb /passes/memory/memory_map.cc | |
| parent | a2d053694b6269bab8871a810142943fac6a3a18 (diff) | |
| download | yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.tar.gz yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.tar.bz2 yosys-93a70959f3f67ffcee8159b18a5f68904e32a074.zip | |
Replaced RTLIL::Const::str with generic decoder method
Diffstat (limited to 'passes/memory/memory_map.cc')
| -rw-r--r-- | passes/memory/memory_map.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 1651751a2..45c3933c3 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -138,7 +138,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\D"] = data_reg_in.back(); RTLIL::Wire *w_out = new RTLIL::Wire; - w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].str.c_str(), i); + w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); if (module->wires.count(w_out->name) > 0) w_out->name = genid(cell->name, "", i, "$q"); w_out->width = mem_width; |