iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fitting help messages to 80 character width	KrystalDelusion	2022-08-24	1	-2/+2
*	Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.	Marcelina Kościelnicka	2022-06-02	1	-4/+15
*	memory_dff: Add support for no_rw_check attribute.	Marcelina Kościelnicka	2022-06-02	1	-0/+10
*	FfData: some refactoring.	Marcelina Kościelnicka	2021-10-07	1	-1/+1
*	kernel/ff: Refactor FfData to enable FFs with async load.	Marcelina Kościelnicka	2021-10-02	1	-7/+15
*	memory_dff: Recognize soft transparency logic.	Marcelina Kościelnicka	2021-08-13	1	-7/+451
*	memory_dff: Recognize read ports with reset / initial value.	Marcelina Kościelnicka	2021-08-11	1	-7/+0
*	kernel/mem: Introduce transparency masks.	Marcelina Kościelnicka	2021-08-11	1	-1/+2
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Add new helper class for merging FFs into cells, use for memory_dff.	Marcelina Kościelnicka	2021-05-23	1	-237/+104
*	memory_dff: Use Mem helper.	Marcelina Kościelnicka	2021-05-21	1	-19/+26
*	memory_dff: Remove now-useless write port handling.	Marcelina Kościelnicka	2021-03-08	1	-71/+7
*	memory_dff: Remove code looking for $mux cells.	Marcelina Kościelnicka	2021-03-08	1	-56/+12
*	memory_dff: Fix needlessly duplicating enable bits.	Marcelina Kościelnicka	2020-10-22	1	-0/+8
*	memory_dff: Refactor to use FfInitVals.	Marcelina Kościelnicka	2020-07-24	1	-12/+5
*	memory_dff: recognize more dff cells	Marcelina Kościelnicka	2020-07-23	1	-11/+112
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-46/+46
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-8/+8
*	Make liberal use of IdString.in()	Eddie Hung	2019-08-06	1	-1/+1
*	memory_dff: Fix checking of feedback mux input when more than one mux	David Shah	2019-07-02	1	-3/+5
*	Fix spacing	Eddie Hung	2019-06-25	1	-4/+3
*	Move only one consumer check outside of while loop	Eddie Hung	2019-06-25	1	-6/+5
*	Walk through as many muxes as exist for rd_en	Eddie Hung	2019-06-24	1	-8/+16
*	memory_dff: Fix typo when checking init value	David Shah	2018-12-18	1	-1/+1
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Disable memory_dff for initialized FFs	Clifford Wolf	2018-05-28	1	-1/+19
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	1	-1/+1
*	Bugfix in memory_dff	Clifford Wolf	2015-10-31	1	-1/+12
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-9/+43
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Modernized memory_dff (and fixed a bug)	Clifford Wolf	2015-06-14	1	-147/+164
*	Merge clock inverters in memory_dff	Clifford Wolf	2015-06-09	1	-16/+37
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-6/+10
*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16	1	-4/+6
*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-19/+19
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-15/+11
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-7/+2
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-4/+7
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-19/+19
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-19/+19
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+4
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1