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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /passes/memory/memory_dff.cc | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'passes/memory/memory_dff.cc')
| -rw-r--r-- | passes/memory/memory_dff.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index be4b3c100..abbffa7d6 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -189,9 +189,9 @@ struct MemoryDffWorker do { bool enable_invert = mux_cells_a.count(sig_data) != 0; Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"))); - sig_data = sigmap(mux->getPort("\\Y")); - en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); + check_q.push_back(sigmap(mux->getPort(enable_invert ? ID::B : ID::A))); + sig_data = sigmap(mux->getPort(ID::Y)); + en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort(ID::S)) : mux->getPort(ID::S)); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); for (auto bit : sig_data) @@ -259,12 +259,12 @@ struct MemoryDffWorker if (cell->type == "$dff") dff_cells.push_back(cell); if (cell->type == "$mux") { - mux_cells_a[sigmap(cell->getPort("\\A"))] = cell; - mux_cells_b[sigmap(cell->getPort("\\B"))] = cell; + mux_cells_a[sigmap(cell->getPort(ID::A))] = cell; + mux_cells_b[sigmap(cell->getPort(ID::B))] = cell; } - if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_y = cell->getPort("\\Y"); + if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort(ID::A)) == 1)) { + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_y = cell->getPort(ID::Y); if (cell->type == "$not") sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool()); if (cell->type == "$logic_not") |