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author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
commit | c094c53de83707a5bf1b268640283f1dde235873 (patch) | |
tree | 27e480f63e0d34d8cbfcf8fcf29472c198381296 /passes/memory/memory_dff.cc | |
parent | 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff) | |
download | yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.gz yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.bz2 yosys-c094c53de83707a5bf1b268640283f1dde235873.zip |
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'passes/memory/memory_dff.cc')
-rw-r--r-- | passes/memory/memory_dff.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index b1f1e22b5..56915776e 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -69,7 +69,6 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI replaced_this_bit:; } - sig.optimize(); return true; } |