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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-2/+2
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-021-4/+15
* memory_dff: Add support for no_rw_check attribute.Marcelina Kościelnicka2022-06-021-0/+10
* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-1/+1
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-7/+15
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-131-7/+451
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-111-7/+0
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-111-1/+2
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-231-237/+104
* memory_dff: Use Mem helper.Marcelina Kościelnicka2021-05-211-19/+26
* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-081-71/+7
* memory_dff: Remove code looking for $mux cells.Marcelina Kościelnicka2021-03-081-56/+12
* memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+8
* memory_dff: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-12/+5
* memory_dff: recognize more dff cellsMarcelina Kościelnicka2020-07-231-11/+112
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-46/+46
* kernel: use more ID::*Eddie Hung2020-04-021-8/+8
* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
* memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-021-3/+5
* Fix spacingEddie Hung2019-06-251-4/+3
* Move only one consumer check outside of while loopEddie Hung2019-06-251-6/+5
* Walk through as many muxes as exist for rd_enEddie Hung2019-06-241-8/+16
* memory_dff: Fix typo when checking init valueDavid Shah2018-12-181-1/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Disable memory_dff for initialized FFsClifford Wolf2018-05-281-1/+19
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed some visual studio warningsClifford Wolf2016-02-131-1/+1
* Bugfix in memory_dffClifford Wolf2015-10-311-1/+12
* Added read-enable to memory modelClifford Wolf2015-09-251-9/+43
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Modernized memory_dff (and fixed a bug)Clifford Wolf2015-06-141-147/+164
* Merge clock inverters in memory_dffClifford Wolf2015-06-091-16/+37
* namespace YosysClifford Wolf2014-09-271-6/+10
* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-161-4/+6
* Various improvements in memory_dff passClifford Wolf2014-08-061-21/+22
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-19/+19
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-15/+11
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-7/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+7
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-19/+19
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-19/+19
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-1/+0
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-8/+4
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1